1Self-Repair as long as Robust System DesignYanjing LiIntel LabsStan as long as d UniversityHard

1Self-Repair as long as Robust System DesignYanjing LiIntel LabsStan as long as d UniversityHard www.phwiki.com

1Self-Repair as long as Robust System DesignYanjing LiIntel LabsStan as long as d UniversityHard

Burroughs, Wayne, Morning Show Host and Music Director has reference to this Academic Journal, PHwiki organized this Journal 1Self-Repair as long as Robust System DesignYanjing LiIntel LabsStan as long as d UniversityHardware Failures: Major Concern2Permanent: our focusTemporaryTolerating Permanent Hardware Failures3DetectionRecovery

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4DetectionRecoveryConcurrent error detection: expensiveTolerating Permanent Hardware Failures5DetectionRecoveryOnline Self-Test in addition to DiagnosticsNon-continuous Low powerConcurrent No visible downtimeTolerating Permanent Hardware Failures6DetectionRecoveryOnline Self-Test in addition to DiagnosticsLocalize failuresTolerating Permanent Hardware FailuresDiagnosis

7DetectionRecoverySelf-repairReplace / bypass faulty component(s)Tolerating Permanent Hardware Failures8DetectionRecoveryCorrection of corrupted data in addition to states Failure occursRollbackCheckpointFailure detectedTolerating Permanent Hardware Failures9DetectionRecoveryThis Lecture

Outline10IntroductionSelf-repair techniques Memories Processor cores Uncore componentsConclusionMemory Organization11Sense amplifiersRow decoderColumn decoderData registersrd/wr logicaddrendata-indata-outColumn multiplexersMemory Functional Fault Models12Memory cell array faults stuck-at, transition, coupling, etc. Address decode faults (AFs) no cell accessed, multiple cells accessed, etc. Read/write logic faults Equivalent to memory cell array faultsSingle bit / word / column / row faults dominate[Aitken 04, Kurdahi 06, Sridharan 12]

Spare Rows / Columns13Spare columnSense amplifiersRow decoderColumn decoderData registersrd/wr logicaddrendata-indata-outSpare rowsColumn multiplexers14Sense amplifiersRow decoderColumn decoderData registersrd/wr logicaddrendata-indata-outColumn multiplexersMemory Self-Repair Using Spare RowsRow decoder modified15Sense amplifiersRow decoderColumn decoderData registersrd/wr logicaddrendata-indata-outColumn multiplexersMemory Self-Repair Using Spare ColumnsAdditional multiplexers in addition to select logic MultiplexersSelf-repair control

Spare Words16Sense amplifiersRow decoderColumn decoderData registersrd/wr logicaddrendata-indata-outColumn multiplexersSpare words poolSame inputs as RAMSelf-repair control[Kim 98]Redundancy in Memories17Essential to improve yield in addition to reliability Widely used in commercial RAMs Related topics How much redundancy Built-in repair analysis: redundancy allocation18How Much Redundancy

19Yield analysis in addition to yield learning Example: negative binomial memory yield model How Much Redundancy20Spare rows in addition to columns NP complete Various algorithms in addition to EDA tools existBuilt-In Repair AnalysisSpecial Self-Repair Techniques as long as Caches21Caches: affects per as long as mance, NOT functionalityBlock addressTagIndexBlock offsetDecoderVTagData / ECC =Hit/missData out

Cache Line Disable/Delete22Exist in commercial systems Intel [Chang 07], IBM [S in addition to a 08], etc.Block addressTagIndexBlock offsetDecoderVTagData / ECC =Hit/missData outFTFault-tolerance bitSetting the FT Bit23Cache line readECC calculate in addition to checkECC errorCorrect in addition to flag error; log faulty locationECC error at same location already occurred within a time threshold Set FT bit YesYesDoneNoNoPADded Cache24Reconfigurable cache with programmable decoderConventional decoder

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PADded Cache25Reconfigurable cache with programmable decoder Additional tag bits neededProgrammable decoder~ 5% area cost 16KB, direct-mapped, 1-level programmability Reduce cost at the price of granularity[Shirvani 99]Cache Line Delete vs. PADded Cache26Outline27IntroductionSelf-repair techniques Memories Processor cores Uncore componentsConclusion

Core Sparing28Utilize multi-/many-core architectures Core disabling also possibleAlready in commercial products IBM BlueGene/Q Nvidia Ge as long as ce Cisco Metro Fine-grained approachesCore Cannibalization29Many-core designs with small in-order cores 3.5% area cost (OpenRISC 1200)[Romanescu 08]Core Cannibalization: Discussion30What about diagnosisRouting per as long as mance impact Additional wire delay pipeline stages Modified branch resolution, bypass logic, etc. Decreased clock frequencySmall vs. large number of faulty cores

References85[S in addition to a 08] S in addition to a, P.N, et al., “Fault-Tolerant Design of the IBM Power6 Microprocessor,” IEEE Micro, vol. 28, no. 2, pp. 30-38, 2008.[Schuchman 05] Schuchman, E., in addition to T.N. Vijaykumar, “Rescue: A Microarchitecture as long as Testability in addition to Defect Tolerance,” Proc. Intl. Symp. on Computer Architecture, pp. 160-171, 2005.[Shirvani 99] Shirvani, P.P., in addition to E.J. McCluskey, “PADded Cache: A New Fault-Tolerance Technique as long as Cache Memories,” Proc. VLSI Test Symp., pp. 440-445, 1999.References86[Shivakumar 03] Shivakumar, P., et al., “Exploiting Microarchitectural Redundancy as long as Defect Tolerance,” Proc. Intl. Conf. on Computer Design, pp. 481-488, 2003.[Sridharan 12] Sridharan, V., et al., “A Study of DRAM Failures in the Field,” Proc. Intl. Conf. High Per as long as mance Computing, Networking, Storage in addition to Analysis, pp. 1-11, 2012.[Schuchman 05] Schuchman, E., in addition to T.N. Vijaykumar, “Rescue: A Microarchitecture as long as Testability in addition to Defect Tolerance,” Proc. Intl. Symp. on Computer Architecture, pp. 160-171, 2005.

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