A Fast Block Structure Preserving Model Order Reduction as long as Inverse Inductance C
Del Greco, Al, Host has reference to this Academic Journal, PHwiki organized this Journal A Fast Block Structure Preserving Model Order Reduction as long as Inverse Inductance Circuits Hao Yu, Yiyu Shi, Lei He Electrical Engineering Dept. UCLA David Smart Analog Devices Inc. Partially supported by NSF, SRC in addition to UC-MICRO fund Loop inductance Where is the return path Current return paths are not known as a priori How to stamp a loop inductance together with other devices in the same loop to the circuit matrix Partial inductance by PEEC [Rueli:TMTT74] is one choice as long as inductive interconnect Challenge to Model Inductance PEEC Model as long as Interconnect No need to determine return path But did we really solve the problem Partial inductance is associated with every piece of branch current Mutual couplings are everywhere L matrix is dense in addition to not diagonal dominant A fast simulator needs a sparse stamping of devices Sparsifying L by truncation leads to the loss of stability Stamping inverse inductance (L-1) element is an alternative solution L-1 is similar to the diagonal dominant capacitance (C) [Devgan:ICCAD02], in addition to hence it is easy to sparsify How to stamp it correctly in circuit matrix How to further reduce it by model order reduction
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Inverse Inductance Element Simulation First-order stamping in addition to reduction by modified nodal analysis (MNA) Directly stamping leads to a non-passive model [Zheng et.al.:ICCAD02] Double inversion based stamping [Chen,et.al.: ICCAD03] needs an extra cost to invert L matrix Outline Background of Circuit Stamping VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model BVOR Method using BBD (Bordered-block-diagonal) Representation Experimental Results Conclusions Modified Nodal Analysis
Stamping of L-Inverse in Circuit Matrix How to Easily Have a Singular Stamping Why do we need branch current variable as long as inductance The inductor is shorted at dc v2 in addition to v3 are not independent anymore Need a new constraint by adding a new row as long as i1 Outline Background of Circuit Stamping VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model BVOR Method using BBD (Bordered-block-diagonal) Representation Experimental Results Conclusions
Vector Potential Equivalent Circuit Differential Maxell equation VPEC circuit equation describes L-1 elements using branch variables (ii, vi) This leads to the proof that L-1 matrix is diagonal dominant [Yu-He:TCAD05] VNA Stamping Using both branch in addition to nodal variables, VPEC circuit equation leads to a new circuit stamping as long as L-1 The resulting VNA state matrix is non-singular in addition to passive A Circuit Example
VNA Reduction (VOR) The simple first-order model order reduction such as PRIMA [Odabasioglu,et.al:TCAD98] can be applied Find a small dimensioned in addition to orthnormalized matrix V to reduce the original system size by projection If V contains the subspace of moments, the reduced system can match the original system Advantages of VNA Reduction The reduced model is passive Sufficient conditions as long as passivity: The VNA reduction can be per as long as med at dc (s0=0), in addition to hence the path tracing algorithm [Odabasioglu,et.al:TCAD98] can be used as long as efficient reduction Outline Background of Circuit Stamping VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model BVOR Method using BBD (Bordered-block-diagonal) Representation Experimental Results Conclusions
Two Level Decomposition by Branch Tearing A flat presentation of VNA does not show hierarchy in addition to hence leads to a globalized reduction in addition to simulation It is not efficient as long as large-scale circuit with inductance Path-tracing [Odabasioglu,et.al:TCAD98] is only effective as long as tree-links but not as long as general network BBD Representation The resulting system is in fact a bordered-block-diagonal (BBD) state matrices Each block Yi is described by a set of VNA variables (vn, Al) The global block Z0 is described by a set of torn branch variables (ib) BVOR: Localized Reduction BBD representation enables a localized model order reduction Each block Yi (Gi, Ci, Bi) can be reduced locally The last block is purely composed by coupling branches, which is projected by an identity matrix Reduced model is not only passive but also sparse, in addition to it can be analyzed hierarchically
Outline Background of Circuit Stamping VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model BVOR Method using BBD (Bordered-block-diagonal) Representation Experimental Results Conclusions Wave as long as m Comparison (1) Frequency/time domain wave as long as m comparison of full-MNA, SAPOR [Su et.al:ICCAD04] in addition to VNA reduction (VOR) The reduced models are exp in addition to ed close to dc (s0 = 10Hz) with order 80 VOR in addition to original are visually identical in both time/frequency domain SAPOR has larger frequency-domain error in addition to can not converge in time-domain simulation Wave as long as m Comparison (2) Frequency domain wave as long as m in both low in addition to high frequency range The reduced models are exp in addition to ed at s0 = 1GHz with order 80 VOR is identical to the original in both ranges, But SAPOR has large error in low-frequency range.
BBD Structure Preserving BBD (two-level decomposition) representation in addition to reduction of G in addition to C matrices The reduced model has preserved sparsity in addition to BBD structure Runtime Scalability Study of BVOR Compared to SAPOR, BVOR (BBD reduction) is 23X faster to build, 30X faster to simulate, in addition to has 51X smaller error Compared to VOR, BVOR is 12X faster to build, 30X faster to simulate Conclusions in addition to Future Work Propose a new circuit stamping (VNA) as long as L-inverse element, which is passive in addition to non-singular Apply a bordered-block-diagonal (BBD) structured reduction, which enables a localized model order reduction as long as large scale RCL-1 circuits We are planning to extend the structured reduction to h in addition to le nonlinear system
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