Chapter 28 Fabrication of Microelectronic Devices Parts Made by Chapter 28 Proce

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Chapter 28 Fabrication of Microelectronic Devices Parts Made by Chapter 28 Proce

Carlson, Randy, Host has reference to this Academic Journal, PHwiki organized this Journal Chapter 28 Fabrication of Microelectronic Devices Parts Made by Chapter 28 Processes (a) (b) (c) Figure 28.1 (a) A completed eight-inch wafer with completed dice. (b) A single chip in a ball-grid array (BGA) with cover removed. (c) A printed circuit board. Source: Courtesy of Intel Corporation. Fabrication of Integrated Circuits Figure 28.2 Outline of the general fabrication sequence as long as integrated circuits.

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Fabrication of MOS Transistor Figure 28.3 Cross-sectional views of the fabrication of a MOS transistor. Source: After R. C. Jaeger. Allowable Particle Size Counts as long as Clean Rooms Figure 28.4 Allowable particle size counts as long as different clean room classes. Crystallographic Structure in addition to Miller Indices as long as Silicon Figure 28.5 Crystallographic structure in addition to Miller indices as long as silicon. (a) Construction of a diamond-type lattice from interpenetrating face-centered cubic-cells; one of eight penetrating cells is shown. (b) Diamond-type lattice of silicon; the interior atoms have been shaded darker than the surface atoms. (c) Miller indices as long as a cubic lattice.

Finishing Operations on a Silicon Ingot to Produce Wafers Figure 28.6 Finishing operations on a silicon ingot to produce wafers (a) sawing the ends off the ingot; (b) grinding of the end in addition to cylindrical surfaces of a silicon ingot; (c) machining of a notch or flat; (d) slicing of wafers; (e) end grinding of wafers; (f) chemical-mechanical polishing of wafers. CVD Diagrams Figure 28.7 Schematic diagrams of (a) a continuous, atmospheric-pressure CVD reactor in addition to (b) a low-pressure CVD. Source: After S. M. Sze. Silicon Dioxide Growth Figure 28.8 Growth of silicon dioxide showing consumption of silicon. Source: After S. M. Sze.

General Characteristics of Lithography Techniques Figure 28.9 Comparison of lithography techniques. Spinning of Organic Coating on Wafer Figure 28.10 Spinning of an organic coating on a wafer. Techniques of Pattern Transfer Figure 28.11 Schematic illustration of (a) wafer stepper technique to pattern transfer in addition to (b) step- in addition to -scan technique.

Pattern Transfer by Photolithography Figure 28.12 Pattern transfer by photolithography. Note that the mask in Step 3 can be a positive or negative image of the pattern. SCALPEL Process Figure 28.13 Schematic illustration of the SCALPEL process. Moore’s Law Figure 28.14 Illustration of Moore’s law. Source: After M. Madou.

General Characteristics of Silicon Etching Operations Comparison of Etch Rates Etching Directionality Figure 28.15 Etching directionality. (a) Isotropic etching: etch proceeds vertically in addition to horizontally at approximately the same rate, with significant mask undercut. (b) Orientation-dependant etching (ODE): etch proceeds vertically, terminating on {111} crystal planes with little mask undercut. (c) Vertical etching: etch proceed vertically with little mask undercut. Source: Courtesy of K. R. Williams, Agilent Laboratories.

Etch Rates of Silicon Figure 28.16 Etch rates of silicon in different crystallographic orientations using ethylene-diamine/pyrocatechol-in-water as the solution. Source: After Seidel, H. et al., Journal Electrochemical Society, 1990, pp. 3612-3626. Application of Boron Etch Stop in addition to Back Etching to Form Membrane in addition to Orifice Figure 28.17 Application of a boron etch stop in addition to back etching to as long as m a membrane in addition to orifice. Source: After Brodie, I., in addition to Murray, J.J., The Physics of Microfabrication, Plenum Press, 1982. Machining Profiles Associated with Dry-Etching Figure 28.18 Machining profiles associated with different dry-etching techniques: (a) sputtering; (b) chemical; (c) ion-enhanced energetic; (d) ion-enhanced inhibitor. Source: After M Madou.

Etching Figure 28.19 (a) Schematic illustration of reactive plasma etching. (b) Examples of deep reactive-ion etched trench. Note the periodic undercuts or scallops. (c) Near-vertical sidewalls produced through DRIE with an anisotropic-etching process. (d) An examples of cryogenic dry etching showing a 145-m deep structure etched into silison using a 2.0- m thick oxide masking layer. The substrate temperature was -140°C during etching. Source: (a) After M. Madou. (d) After R. Kassing in addition to I.W. Rangelow, University of Kassel, Germany. Holes Generated from Square Mask Figure 28.20 Various holes generated from a square mask in: (a) isotropic (wet) etching; (b) orientation-dependant etching (ODE); (c) ODE with a larger hole; (d) ODE with a rectangular hole; (e) deep reactive-ion etching; in addition to (f) vertical etching. Source: After M. Madou. Ion Implantation Apparatus Figure 28.21 Schematic illustration as long as an apparatus as long as ion implantation.

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PN-Junction Diode Fabrication Figure 28.22 Fabrication sequence as long as a pn-diode. Interconnection of Integrated Circuit Hierarchy Figure 28.23 Connections between elements in the hierarchy as long as integrated circuits. Two-Level Metal Interconnect Structures Figure 18.24 (a) Scanning electron microscope (SEM) photograph of a two-level metal interconnect. Note the varying surface topography. (b) Schematic illustration of a two-level metal interconnect structure. Source: (a) Courtesy of National Semiconductor Corporation. (b) After R. C. Jaeger.

Wire Bonds Connecting Package Leads to Die Bonding Pads Figure 18.25 (a) SEM photograph of wire bonds connecting package leads (left-h in addition to side) to die bonding pads. (b) in addition to (c) Detailed views of (a). Source: Courtesy of Micron Technology, Inc. (a) (b) (c) Thermosonic Welding of Gold Wires Figure 28.26 Schematic illustration of thermosonic welding of gold wires from package leads to bonding pads. IC Packages Figure 28.27 Schematic illustration of various IC packages: (a) dual-in-line package (DIP); (b) flat, ceramic package; (c) common surface-mount configurations; (d) ball-grid arrays.

Flip-Chip Technology Figure 28.28 Illustration of flip-chip technology. Flip-chip package with (a) solder-plated metal balls in addition to pads on the printed circuit board; (b) flux application in addition to placement; (c) reflow soldering; (d) encapsulation. Circuit Board Structures in addition to Features Figure 28.29 Printed circuit board structures in addition to design features.

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