Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, in addition to Anal

Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, in addition to Anal www.phwiki.com

Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, in addition to Anal

Finebaum, Paul, Host has reference to this Academic Journal, PHwiki organized this Journal Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, in addition to Analysis Yu Cai1, Erich F. Haratsch2 , Onur Mutlu1 in addition to Ken Mai1 DSSC, ECE Department, Carnegie Mellon University LSI Corporation Evolution of NAND Flash Memory Flash memory widening its range of applications Portable consumer devices, laptop PCs in addition to enterprise servers Seaung Suk Lee, “Emerging Challenges in NAND Flash Technology”, Flash Summit 2011 (Hynix) CMOS scaling More bits per Cell Reliability in addition to Endurance Challenges as long as NAND Flash Memories Endurance continues to deteriorate Only a few thous in addition to reliable P/E cycles of NAND Flash memory Error correction capability requirements of ECC keep increasing Big gap between MLC flash endurance in addition to storage reliability requirements Enterprise storage needs >50k P/E cycles

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Future NAND Flash Storage Architecture Error Correction Raw Bit Error Rate Hamming codes BCH codes Reed-Solomon codes LDPC codes Other Flash friendly codes BER < 10-15 Need to underst in addition to NAND flash error patterns Read voltage adjusting Data scrambler Data recovery Soft-in as long as mation estimation Noisy Test System Infrastructure Host USB PHY USB Driver Software Plat as long as m USB PHYChip Control Firmware FPGA USB controller NAND Controller Signal Processing Wear Leveling Address Mapping Garbage Collection Algorithms ECC (BCH, RS, LDPC) Flash Memories Reset Erase block Program page Read page NAND Flash Testing Plat as long as m Virtex-V FPGA (NAND Controller) 3x-nm NAND Flash NAND Flash Usage in addition to Error Model (Page0 - Page128) Program Page Erase Block Testing Methodology Erase errors Count the number of cells that fail to be erased to “11” state Program interference errors Compare the data immediately after page programming in addition to the data after the whole block being programmed Read errors Continuously read a given block in addition to compare the data between consecutive read sequences Retention errors Compare the data read be as long as e retention in addition to after retention Characterize short term retention errors under room temperature Characterize long term retention errors by baking in the oven under 125 Flash Error Rates Comparison Error rate increases with P/E cycles Retention errors are the most dominant errors Retention error rates increase as retention time increase Retention Error Mechanism LSB/MSB Electrons loss from the floating gate causes retention errors Cells with more programmed electrons suffer more from retention errors Threshold voltage is more likely to shift one interval than multiple intervals Vth REF1 REF2 REF3 Erased Fully programmed Stress Induced Leakage Current (SILC) Floating Gate Retention Error Value Dependency (3 months) Cells with more programmed electrons tend to suffer more from retention noise (i.e. 00 in addition to 01) 2-bit MLC Background Overview Internal Architecture of 2-bit NAND Flash Memory Retention Error Location Dependency LSB page has less BER Even pages have less BER Vth 11 10 01 00 REF1 REF2 REF3 LSB/MSB Program interference LSB/MSB Program interference errors are caused by extra electrons injection when programming neighbor cells Cells with less programmed electrons suffer more from interference errors Threshold voltage is less likely to shift up more than one level VT REF1 REF2 REF3 Erased Fully programmed Floating Gate Additional Electrons Injected Program Interference Error Value Dependency Cells with less programmed electrons tend to suffer more from neighboring cell interference (i.e. 11 in addition to 10) Program Interference Error Location Dependency Program interference errors appear in even-MSB pages BER of bottom pages are orders of magnitude higher Write Interference on bottom wordline Potential of drain edge of SGS transistor is raised by channel boosting Electrons are accelerated between SGS in addition to WL0 in addition to are quite possible to injected into the floating gate of WL0 HCI noise generated by source/drain hot-electrons in WL0 Threshold voltage of cells on WL0 shift right in addition to it can even shift across more than one level (e.g. 11->01 or 00) SGS WL0 WL31 SGD GND 10 V 0 V 0 V Vpass(10V) WL n Vpgm(20V) Vpass(10V) Vdd bitline Vdd Channel Voltage Read Error Analysis Erased Fully programmed Floating Gate

Erase Errors Analysis n+ n+ 0 V +18 V Continuous erases can significantly reduce errors remove residual electrons Conclusions & Future work Flash errors could show up as long as any operations Erase error, program error, retention error in addition to read error Retention errors are the most dominant errors Flash errors show explainable error patterns Cycle-dependency, value-dependency in addition to location-dependency Underst in addition to ing of modern flash memory error patterns will enable designing effective error tolerance mechanisms Value-asymmetry aware coding techniques Cell location-aware wear leveling mechanisms

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