Finding the root cause of ESD problems Dr. David Pommerenke With contributions f

Finding the root cause of ESD problems Dr. David Pommerenke With contributions f

Finding the root cause of ESD problems Dr. David Pommerenke With contributions f

Johnston, Betty, Freelance Columnist has reference to this Academic Journal, PHwiki organized this Journal Finding the root cause of ESD problems Dr. David Pommerenke With contributions from all members of the EMC laboratory University Missouri Rolla – EMC laboratory ESD is combines many tests in one test ESD failure analysis Susceptibility scanning Voltage in traces during ESD testing Content Definitions Hard-error: Any error that leads to a physical failure of the IC. (Excessive leakage current, loss of functionality) Soft-error: Any error that can be cured by resetting the system (logical errors: bit error, false reset)

Golf Academy of America-Farmers Branch TX

This Particular University is Related to this Particular Journal

Physical parameters that may lead to an ESD failure ESD combines many different tests into one test st in addition to ard. From electrostatics, via breakdown physics to a 1 GHz 20kV/m pulse. It failed, what now Is it a soft or a hard failure At which test point did it fail At which voltage did it fail Was it in contact or air discharge mode How repeatable is the failure It has failed! – What to do now Question: What do you do to debug ESD problems How to fix it Exact circuit underst in addition to ing Pro: The most cost efficient solution. Learn how to design in the future. Contra: Need to underst in addition to software Need to underst in addition to circuits Requires specialized equipment May require special firmware Shielding Pro: No system underst in addition to ing needed. If it works, the fast! Contra: Often more expensive solution Adds material But how to do it

20mm 50mm 200mm @ 8kV, restart @ 10kV restart @ 15kV restart EUT display Local probing around the EUT A first start of finding the root cause may be: Locating sensitivity on the outside might help to correlate to the affected IC or trace, but: Outside location may only be a result of breach in shielding Outside location is too broad to correlate to details inside: Let’s go inside! Different coupling mechanisms require different probes Injection can be done: To the enclosure To cables To connectors To boards To board traces To lead-frames traces – dm – cm – mm – cm2 – 5 mil (using microscope) – 1 mil (using microscope) Probes used as long as injection

Different coupling mechanisms require different probes Direct injection between to “grounds”. In selecting the right injection method one has to try to emulate the same excitation mechanism as occurs during the st in addition to ardized test or at the customer site. Anticipating the right method is often guided by carefully observing the differences of failure signature at different test points. Disturbance sources: TLP in addition to narrow pulse The measurement of the high voltage transmission line pulse generator output pulse, about 500 ps rise (20-80%) Less than 200 ps pulse Narrow pulse generator Automated Susceptibility Scanning system of UMR Brief explanation The system moves injection probes to predefined locations, injects pulses in addition to observes the system response. In most cases, pulses are “ESD-like”, e.g., having rise times 0.1 -2 ns. Injection is done using different injection probes as long as testing direct coupling, E in addition to H-field coupling. If needed, the voltages at the input of the IC are measured during the ESD event.

Automated Susceptibility Scanning system of UMR Critical is the error feedback: A test code needs to be operating on the EUT. The test code signals to the control PC if a malfunction has occurred. If so, the level of injected noise (by source setting, not by induced voltage) is recorded in addition to the EUT is reset. Test flow diagram Example: Identifying sensitive nets Besides direct coupling to an IC, four sensitive nets are identified Only 4 nets are sensitive, but there sensitivity is 10X as strong as any other net Net 1 Net 2 Net 3 Net 4 Net 1 Net 2 Net 3 Net 4

The same area is scanned using different polarization of the H-field probe. The difference between the “left” in addition to the “right” polarization is the polarity of the induced noise voltage. The sensitive traces are identified by circuit diagram. If needed a finer scan is per as long as med. Example: Identifying sensitive nets A critical part of the board in the previous scanned area has been fine-scanned using very small magnetic field probe to identify the correct trace The scan resolution was set to 0.5mm x 0.5mm The small probe couples less energy into the trace, but in a highly localized area Example: Identifying sensitive nets Net 1 Net 2 Net 2 Net 3 After comparing the identified sensitive nets with PCB layout, three nets have been identified to be sensitive to ESD The sensitivity of those nets have been quantified in terms of applied voltage in the HV generator Induced current direction on the each sensitive net has been identified Modification to a sensitive net

TX RX 100ohm 330pF Filter Location Modification to a sensitive net Simple Low Pass Be as long as e After Filter location Modification to a sensitive net Scanned Area Medium Magnetic Probe The top side of the PCB is scanned using the medium size magnetic probe with four different polarization Some sensitive areas on the IC are identified Direct coupling to ICs

Direct coupling to ICs Signal couples directly into the IC IC reacts to narrow pulses much narrower than the intended signals 300ps For such an ICs, no PCB or shielding solution is economical. Scanning can identify such situations in addition to help to verify improvements in the IC design, packaging (e.g., flip-chip) or the control software. In our experience, direct coupling to ICs is growing problem: Fast IC process technology is used more in addition to more in badly shielded products. Coupling to PCBs is reduced by burried layers in addition to traces Dense PCBs have hardly any traces visible (BGA packages) New is better, well . Shown are the voltage settings of a pulse generator at which an upset occurs if A narrow pulse (less than 300 ps width at 50% amplitude) is causing an upset of the IC. Note: the new IC per as long as med worse! Worsening ESD soft-error per as long as mance is a significant risk if new processes are introduced, or if I/O structures are modified. Voltages on traces

Johnston, Betty North County Times - Fallbrook Office Freelance Columnist

Semi rigid coax cable, connected to 20GS/sec 6 GHz b in addition to width scope 470 Ohm GND VIA (close to the Trace) How measure in-circuit while pulsing The trace is loaded by 470 + 50 Ohm. The small loop area ensures little dB/dt coupling in addition to good frequency response of the probing method. Three traces have been isolated by terminating/filtering circuits Double pulse has been eliminated The reset line still reacts to this narrow pulse (the system crashed) It has been shown that the IC of interest is causing the crash, reacting to a very narrow pulse Very Narrow pulse on slow status line (< 150ps) leads to crash Voltages on a status line Clock-N Clock-P Pulse has been applied repeatedly, increasing the voltage until system crashes Wave as long as ms are recorded (20 GHz / 6 Gsample/sec). Differential clock ESD Event on differential clock Very sensitive to noise during the transition ESD Event on differential clock No crash! + - Clock-N Clock-P Differential input has an offset The result is repeatable. Increasing difference should not lead to a system crash. Why Noise increased differential voltage IC ESD System level ESD Consequence St in addition to ard Voltage DUT Operating Application method Tested properties When does it occur Destructive CDM / HBM / MM Typically < 3000 IC, sub system System is not powered Direct to the IC PINs IC protection circuits Manufacturing, h in addition to ling Destructive in addition to Upset IEC 61000-4-2 Typically < 15 000 System System is operating Enclosure, PINs System design Qualification tests, Customer site IC in addition to system level ESD testing The board has been scanned with four different probe polarization (up, down, left, right) to take account of the induced current on the board The medium size magnetic field probe was used with 1.5mm x 1.5mm scan resolution ESD sensitive net can be identified roughly, but the resolution is not so fine enough to pin point a single trace. Example: Identifying sensitive nets

Johnston, Betty Freelance Columnist

Johnston, Betty is from United States and they belong to North County Times – Fallbrook Office and they are from  Fallbrook, United States got related to this Particular Journal. and Johnston, Betty deal with the subjects like Local News

Journal Ratings by Golf Academy of America-Farmers Branch

This Particular Journal got reviewed and rated by Golf Academy of America-Farmers Branch and short form of this particular Institution is TX and gave this Journal an Excellent Rating.