From Crash- in addition to -Recover to Sense- in addition to -Adapt: Our Evolving Models of Computing Machines Computers are Built on STUFF THAT IS IMPERFECT AND Engineers Know How to “S in addition to bag” Uncertainty Means

From Crash- in addition to -Recover to Sense- in addition to -Adapt: Our Evolving Models of Computing Machines Computers are Built on STUFF THAT IS IMPERFECT AND Engineers Know How to “S in addition to bag” Uncertainty Means

From Crash- in addition to -Recover to Sense- in addition to -Adapt: Our Evolving Models of Computing Machines Computers are Built on STUFF THAT IS IMPERFECT AND Engineers Know How to “S in addition to bag” Uncertainty Means

Craig, Cindy, Marketing Director has reference to this Academic Journal, PHwiki organized this Journal From Crash- in addition to -Recover to Sense- in addition to -Adapt: Our Evolving Models of Computing Machines Rajesh K. GuptaUC San Diego.To a software designer, all chips look alikeTo a hardware engineer, a chip is delivered as per contract in a data-sheet.2Computers are Built on STUFF THAT IS IMPERFECT AND Reality is 3

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Changing From Chiseled Objects to Molecular Assemblies4Courtesy: P. Gupta, UCLA45nm Implementation of Leon3 Processor CoreEngineers Know How to “S in addition to bag”5PVTA margins add to guardb in addition to sStatic Process variation: effective transistor channel length in addition to threshold voltageDynamic variations: Temperature fluctuations, supply Voltage droops, in addition to device Aging (NBTI, HCI)Uncertainty Means UnpredictabilityVLSI Designer: Eliminate ItCapture physics into modelsStatistical or plain-old Monte CarloManufacturing, temperature effectsArchitect: Average it outWorkload (Dynamic) VariationsSoftware, OS: Deny ItSimplify, re-organize OS/tasks breaking these into parts that are precise (W.C.) in addition to imprecise (Ave.)6Each doing their own thing, massive overdesign Simulate ‘degraded’ netlist with model input changes (DVth)Deterministic simulations capture known physical processes (e.g., aging)Multiple (Monte-Carlo) simulations wrapped around a nominal model

Let us step back a bit: HW-SW StackHardware Abstraction Layer (HAL)Operating SystemApplicationApplication7Let us step back a bit: HW-SW StackHardware Abstraction Layer (HAL)Operating SystemApplicationApplication8Time or partLet us step back a bit: HW-SW StackHardware Abstraction Layer (HAL)Operating SystemApplicationApplication9Time or part20x in sleep power50% in per as long as mance40% larger chip35% more active power60% more sleep power

What ifHardware Abstraction Layer (HAL)Operating SystemApplicationApplication10Time or partNew Hardware-Software Interface minimal variability h in addition to ling in hardware 11UNO Computing Machines Seek Opportunities based on Sensing ResultsVariability manifestationsfaulty cache bitsdelay variationpower variationVariability signatures:cache bit mapcpu speed-power mapmemory access timeALU error rates12SensorsModelsMetadata Mechanisms: Reflection, Introspection

UnO Computing Machines: Taxonomy of Underdesign13Puneet Gupta/UCLAHardwareSoftwareSeveral Fundamental QuestionsHow do we distinguish between codes that need to be accurate versus that can be not so How fine grain are these (or have to be)How do we communicate this in as long as mation across the stack in a manner that is robust in addition to portable And error controllable (=safe).What is the model of error that should be used in designing UNO machines14Building Machines that leverage move from Crash & Recover to Sense & Adapt15

Expedition Gr in addition to Challenge & Questions“Can microelectronic variability be controlled in addition to utilized in building better computer systems”16Three Goals:Address fundamental technical challenges (underst in addition to the problem)Create experimental systems (proof of concept prototypes)Educational in addition to broader impact opportunities to make an impact (ensure training as long as future talent).What are most effective ways to detect variabilityWhat are software-visible manifestationsWhat are software mechanisms to exploit variabilityHow can designers in addition to tools leverage adaptationHow do we verify in addition to test hw-sw interfacesThrusts traverse institutions on testbed vehicles seeding various projects17Monitor manifestations from instructions levels to task levels.Observe in addition to Control Variability Across StackBy the time, we get to TLV, we are into a parallel software context: instruct OpenMP scheduler, even create an abstraction as long as programmers to express irregular in addition to unstructured parallelism (code refactoring).The steps to build variability abstractions up to the SW layer[ILV,SLV,PLV,TLV] Rahimi et al, DATE’12, ISLPED’12, TC’13, DATE’13

Closer to HW: Uncertainty ManifestationsThe most immediate manifestations of variability are in path delay in addition to power variations.Path delay variations has been addressed extensively in delay fault detection by test community.With Variability, it is possible to do better by focusing on the actual mechanismsFor instance, major source of timing variation is voltage droops, in addition to errors matter when these end up in a state change.19Combine these two observations in addition to you get a rich literature in recent years as long as h in addition to ling variability induced errors: Razor, EDA, TRC, Detecting in addition to Correcting Timing ErrorsDetect error, tune supply voltage to reach an error rate, borrow time, stretch clockExploit detection circuits (e.g., voltage droops), double sampling with shadow latches, Exploit data dependence on circuit delaysEnable reduction in voltage marginManage timing guardb in addition to s in addition to voltage marginsTunable Replica allow non-intrusive operation.20Voltage droopVoltage droopSensing: Razor, RazorII, EDS, Bubble RazorDouble Sampling (Razor I) [Ernest’03] Transition Detector with Time Borrowing [Bowman’09] Razor II [Das’09] Double Sampling with Time Borrowing [Bowman’09] EDS [Bowman ‘11]

Task Ingredients: Model, Sense, Predict, AdaptSense & AdaptObservation using in situ monitors (Razor, EDS) with cycle-by-cycle corrections (leveraging CMOS knobs or replay)22Predict & PreventRelying on external or replica monitors Model-based rule derive adaptive guardb in addition to to prevent errorCHARACTERIZE, MODEL, PREDICTDon’t Fear Errors: Bits Flip, Instructions Don’t Always Execute Correctly23Bit Error Rate, Timing Error Rate, Instruction Error Rate, .Characterize Instructions in addition to Instruction Sequences as long as Vulnerability to timing errorsCharacterize LEON3 in 65nm TSMC across full range of operating conditions: (-40°C125°C, 0.72V1.1V)24Critical path (ns)Dynamic variations cause the critical path delay to increase by a factor of 6.1×.

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Generate ILV, SLV “Metadata”The ILV (SLV) as long as each instructioni (sequencei) at every operating condition is quantified:where Ni (Mi) is the total number of clock cycles in Monte Carlo simulation of instructioni (sequencei) with r in addition to om oper in addition to s. Violationj indicates whether there is a violated stage at clock cyclej or not.ILVi (SLVi) defined as the total number of violated cycles over the total simulated cycles as long as the instructioni (sequencei). Now, I am going to make a jump over characterization data Observe:The execute in addition to memory parts are sensitive to V/T variations, in addition to also exhibit a large number of critical paths in comparison to the rest of processor.Hypothesis: We anticipate that the instructions that significantly exercise the execute in addition to memory stages are likely to be more vulnerable to V/T variations Instruction-level Vulnerability (ILV)VDD= 1.1VT= 125°CConnect the dots from paths to InstructionsFor SPARC V8 instructions (V, T, F) are varied in addition to ILVi is evaluated as long as every instructioni with r in addition to om oper in addition to s; SLVi is evaluated as long as a high-frequent sequencei of instructions.1) Classify Instructions in 3 ClassesInstructions are partitioned into three main classes: (i) Logical & arithmetic; (ii) Memory; (iii) Multiply & divide. The 1st class shows an abrupt behavior when the clock cycle is slightly varied, mainly because the path distribution of the exercised part by this class is such that most of the paths have the same length, then we have all-or-nothing effect, which implies that either all instructions within this class fail or all make it.ILV at 0.88V, while varying temperature:

2) Check them across temperatureILV at 0.72V, while varying temperature: All instruction classes act similarly across the wide range of operating conditions: as the cycle time increases gradually, the ILV becomes 0, firstly as long as the 1st class, then as long as the 2nd class, in addition to finally as long as the 3rd class. For every operating conditionsILV (3rd Class) ILV (2nd Class) ILV (1st Class) 3) Classify Instruction SequencesSLV at (0.81V, 125C)The top 20 high-frequent sequences (Seq1-Seq20) are extracted from 80 Billion dynamic instructions of 32 benchmarks.Sequences are classified into two classes based on their similarities in SLV values: Class I (Seq20) only consists of the arithmetic/logical instructions.Class II (Seq1-Seq19) is a mixture of all types of instructions including the memory, arithmetic/logical, in addition to control instructions.Classification of Sequence of Instructions (2/3)SLV at (0.81V, -40C).Same trend with 165°C temperature variations.For every operating conditions:SLV (Class II) SLV (Class I)Sequences in Class II need higher guardb in addition to s compared to Class I, because in addition of ALU’s critical paths, the critical paths of memory are activated ( as long as the load/store instructions) as well as the critical paths of integer code conditions ( as long as the control instructions).

Ferrari Chip: Closing Loop On-Chip55ARM Cortex-M3JTAGAMBABusGPIOTimersPLLRO CLKConfig64 kB IMEM176 kB DMEMECCCounters8 banks of sensors(N/P Leak, Temp, Oxide)19 DDROsGPIOSensOutOn-Chip Sensors Memory mapped i/o in addition to controlLeakage sensors, DDROs, temperature sensors, reliability sensorsBetter support as long as OS in addition to software55Available since April 2013Sense- in addition to -Adapt Fundamentally Alters The StackMachines that consist of parts with variations in per as long as mance, power in addition to reliabilityMachines that incorporate sensing circuitsMachines w/ interfaces to change ongoing computation & structures New machine models: QOS or Relaxed Reliability parts.56Thank You!57http://variability.orgThe Variability ExpeditionA NSF Expeditions in Computing ProjectRajesh K. GuptaNikil Dutt, UCIPunit Gupta, UCLAMani Srivastava, UCLASteve Swanson, UCSDLara Dolecek, UCLASubhashish Mitra, Stan as long as dYY Zhou, UCSDTajana Rosing, UCSDAlex Nicolau, UCIRanjit Jhala, UCSDSorin Lerner, UCSDRakesh Kumar, UIUCDennis Sylvester, UMichYuvraj Agrawal, CMULucas Wanner, UCLA

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