IPR: In-Place Reconfiguration as long as FPGA Fault Tolerance Outline Soft Error SEU as long as FPGA SER (Soft Error Rate)
Dean, Mike, Freelance Reporter & Photographer has reference to this Academic Journal, PHwiki organized this Journal IPR: In-Place Reconfiguration as long as FPGA Fault Tolerance Zhe Feng1, Yu Hu1, Lei He1 in addition to Rupak Majumdar2 1Electrical Engineering Department 2Computer Science Department University of Cali as long as nia, Los Angeles Present by Zhe Feng Address comments to firstname.lastname@example.org Outline Introduction in addition to motivation Algorithms Experimental Results Conclusions Soft Error Soft errors could be caused by cosmic rays or noise upsets Future devices more vulnerable due to scaling Special session 1E Resilient Computing Two types of soft errors in FPGA Single Event Upset (SEU): Modification of the content of memory bits Single Event Transient (SET): Glitches latched by registers
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SEU as long as FPGA SEU of block memory can be detected in addition to corrected by row-based CRC in addition to ECC SEU of configuration memory can be fixed by Periodical memory scrubbing. Scan-based CRC in addition to ECC Both may be too late, as the circuit function may have been changed. SER (Soft Error Rate) SER is calculated by Monte Carlo simulation under single fault model. In each run, SER is the percentage of clock cycles with observable errors at primary output as long as given test bench The overall SER is the average of all runs. SER 1/ MTTF (mean time to failures) Impact of SEU as long as FPGA FGPA has 10x bigger SER compared to ASIC Due to large configuration memory SEU is one of biggest challenges as long as FPGA-based applications Most FPGAs are used in systems but not prototypes One of the biggest application is internet routers FPGA boards returned after two crashes
FPGA Resynthesis Resynthesis Rewrites the circuit in logic or physical netlist Reconfigures the LUTs (Source: Andrew Ling, University of Toronto, DAC’05) RTL Synthesis Logic Synthesis Technology Mapping Resynthesis Packing P&R ROSE per as long as ms iterative logic trans as long as mations with explicit stochastic yield rate evaluation Logic trans as long as mation by fault tolerance Boolean Matching Boolean Matching Inputs Template H in addition to Boolean function F as long as logic block Fault rates as long as the inputs in addition to the SRAM bits of the template Outputs Either that F cannot be implemented by template H Or the configuration of H to obtain function F ROSE: RObust REsynthesis [ICCAD08] Fault-Tolerant Boolean Matching minimizes the observable faults at the output of the template Need of In-place Logic Optimization ROSE, same as most existing logic optimization techniques, does not preserve the layout (topology) of a circuit design. Interconnect dominates in FPGA In-place resynthesis (IPR) leads to a faster design closure. Minimal or no impact on the physical design
Our Major Contributions Propose an in-place resynthesis algorithm, IPR Maximize the yield rate as long as FPGAs Preserve the topology of the logic network Reduce the runtime complexity compared to other SAT-based approaches IPR reduces the fault rate by 48% in addition to increases MTTF by 1.94X. Compared to the state-of-the-art academic technology mapper Berkeley ABC. With the same area in addition to per as long as mance. Outline Background Algorithms Experimental Results Conclusions IPR: In-place Reconfiguration 0 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 0 0 0 Fault rate = 37.5% Fault rate = 12.5% Maximize identical configuration bits as long as complementary inputs of an LUT. Change the functions of multiple LUTs to guarantee the function of the circuit unchanged.
IPR algorithm Initial Full-chip Functional Simulation Initial Full-chip ODC Mask Calculation Node Criticality Analysis Cone Construction In-place LUT Reconfiguration in addition to Boolean Matching Localize Truth Table Update Localize ODC Mask Update Circuit Analysis Localize Update IPR algorithm Initial Full-chip Functional Simulation Initial Full-chip ODC Mask Calculation Node Criticality Analysis Cone Construction In-place LUT Reconfiguration in addition to Boolean Matching Localize Truth Table Update Localize ODC Mask Update Circuit Analysis Localize Update ODC Mask based Node Criticality 0 1 0 1 1 Logic Network 0 0 1 1 1 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 Primary outputs ODC mask: 1010 (I. Markov, ICCAD07) The ODC mask quantifies the impact of a node on the primary outputs. The criticality of a node is defined as the percentage of ones in the ODC mask, in addition to decides the priority of reconfiguration in IPR.
IPR algorithm Initial Full-chip Functional Simulation Initial Full-chip ODC Mask Calculation Node Criticality Analysis Cone Construction In-place LUT Reconfiguration in addition to Boolean Matching Localize Truth Table Update Localize ODC Mask Update Circuit Analysis Localize Update Cone Construction Select a subset SN of first-order fanout LUTs of n Construct a cone as long as a selected root LUT Root LUT is a fanout of SN Include SN but not its first-order fanins Cut size of the cone is limited a n d c b e Root In-place LUT Reconfiguration The functions of LUTs in the cone are changed to increase of identical configuration pairs But function of input/out nets in addition to topology of internal nets are kept unchanged No change of circuit function in addition to layout a n d c b e Root
In-place Boolean Matching Conjunctive Normal Form (CNF) Truth table can be encoded as follows The cone can be encoded as follows To make a pair of configuration bits (ci, cj) in LUT L symmetric, we have Combining all the three, we have CNF as long as mulation as long as in-place Boolean matching (IP-BM). IP-BM preserves both the logic function in addition to topology of the cone. Outline Background Algorithms Experimental Results Conclusions Experimental Settings in addition to CAD Flows Implemented in C++ in addition to use miniSAT2.0 as the SAT solver Results collected on a Ubuntu workstation with 2.6GHz Xeon CPU in addition to 2GB memory QUIP benchmarks are tested Mapped with 4-LUTs by Berkeley ABC Per as long as m in addition to compare the following synthesis flows: ABC, IPR, ROSE+IPR
Experimental Settings in addition to CAD Flows (Cont) Fault model Uni as long as m soft error rate as long as all configuration bits in LUT but ignore interconnect configuration bits during IPR. Uni as long as m soft error rate as long as all configuration bits in LUT in addition to interconnect during validation. The fault rate of the chip is calculated by Monte Carlo simulation Single fault injection as long as all configuration bits in LUT in addition to interconnect 32k r in addition to om inputs Full-chip Fault Rate by Monte Carlo Simulation 59% fault rate reduction! ABC vs. IPR vs. ROSE+IPR: 1:0.52:0.51 Area (LUT ) ABC vs. IPR vs. ROSE+IPR: 1: 1 : 0.81
Estimation of Mean Time To Failure The best flow in terms of the robustness in addition to area is ROSE+IPR 50x faster! Conclusions We develop an in-place resynthesis algorithm, IPR. Increases MTTF by 2X over ABC; Preserves the topology of the logic network as long as a faster design closure; Complementary to existing fault-tolerant resynthesis algorithms. In the future, we will consider Experiments assume multiple uncorrelated faults in addition to given correlations between faults; Extend IPR with criticality considering interconnects explicitly. Thank You! IPR: In-Place Reconfiguration as long as FPGA Fault Tolerance Zhe Feng, Yu Hu, Lei He in addition to Rupak Majumdar
Backup Slides Criticality as long as Configuration Bit Depends on two criteria: One is a sequence of input vectors as long as the LUT. The other is the ODC mask of the LUT. The criticality of a configuration bit c : In-place Boolean Matching Conjunctive Normal Form (CNF) Truth table can be encoded as follows The cone can be encoded as follows To make a pair of configuration bits (ci, cj) in LUT L symmetric, we have Combining all the three, we have CNF as long as mulation as long as in-place Boolean matching (IP-BM). IP-BM preserves both the logic function in addition to topology of the cone.
IPR Enhancement Iterative (i.e., r in addition to om) algorithm without greedy procedure based on criticality Provide different ordering as long as optimization of gates Without periodic yield rate evaluation With periodic yield rate evaluation Large cut size Increase the opportunity to find the feasible cone. IPR Enhancement (Cont) Extend to MIMO MISO MIMO Increase the opportunity to try more LUTs
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