Manufacturing-Aware Physical Design Andrew B. Kahng Puneet Gupta (Univ. of Calif
Slechta, Ashley, Marketing Assistant has reference to this Academic Journal, PHwiki organized this Journal Manufacturing-Aware Physical Design Andrew B. Kahng Puneet Gupta (Univ. of Calif. San Diego) Outline Challenges DFM Philosophy Manufacturing in addition to Variability Primer Design as long as Value Composability Per as long as mance Impact Limited Fill Insertion Function Aware OPC Systematic Variation Aware STA Futures of Mfg-Aware PD Printing Figures courtesy Synopsys Inc.
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Data Volume Explosion Number of design rules per process node MEBES file size as long as one critical layer vs. technology node RET Layers Explosion Number of design rules per process node 0% 180nm 150nm 130nm 90 nm Source: TSMC Technology Symposium, April 22 2003 Number of TSMC Mask Layers Using OPC/PSM Design Rules Explosion Number of design rules per process node
Variation: Across-Wafer Frequency Variation: Leakage Subthreshold leakage current varies exponentially with threshold voltage: I exp(-Vth) Vth = f(channel length, oxide thickness, doping) Most affected by variations in gate length ±10% Ld ±100% Isub Dennis Sylvester, U. Michigan Outline Challenges DFM Philosophy Manufacturing in addition to Variability Primer Design as long as Value Composability: PSM in addition to Assists Per as long as mance Impact Limited Fill Insertion Function Aware OPC Systematic Variation Aware STA Futures of Mfg-Aware PD
Symptoms: Routing Rules (1) Minimum area rules in addition to via stacking Stacking vias through multiple layers can cause minimum area violations (alignment tolerances, etc.) Via cells can be created that have more metal than minimum via overlap (used as long as intermediate layers in stacked vias) Multiple-cut vias Use multiple-cut vias cells to increase yield in addition to reliability Can be required as long as wires of certain widths Multiple via cut patterns have different spacing rules Four cuts in quadrilateral; five cuts in cross; six cuts in 2×3 array; With wide-wire spacing rules, complicates pin access Cut-to-cut spacing rules check both cut-to-cut in addition to metal-to-metal when considering via-to-via spacing Width- in addition to Length-dependent spacing rules Width-dependent rules: domino effects Variant: parallel-run rule (longer parallel runs more spacing) Measuring length in addition to width: halo rules affect computation Influence rules or stub rules A fat wire, e.g., power/ground net, will influence the spacing rule within its surroundings any wire that is X um away from the fat wire needs to be at least Y um away from any other geometry. Example: fat wire with thin tributaries bigger spacing around every wire within certain distance of the thin tributaries ECO insertion of a tributary causes complications Strange jogs in addition to spreading when wires enter an influenced area Symptoms: Routing Rules (2) Example: LEF/DEF 5.5, April 2003
Example: LEF/DEF 5.5, April 2003 Density Grounded metal fills (dummy fill) Via isodensity rules in addition to via farm rules (via layers must be filled in addition to slotted, have width-dependent spacing rule analogs, etc.) Non-rectilinear (-geometry) routing X-Architecture: http://www.xinitiative.org/ Y-Architecture: http://vlsicad.ucsd.edu/Yarchitecture/ , LSI Logic patents L in addition to ing pad shapes (isothetic rectangle vs octagon vs circle), different spacings (~1.1x) between diagonal in addition to Manhattan wires, etc. More exceptions More non-default classes (timing, EM reliability, ) Not just power in addition to clock >0.25um width may be wide many exceptions Symptoms: Routing Rules (3) Symptoms: Routing Rules Degrade completion rates, runtime efficiency Postprocessing likely no longer suffices E.g., antennas There is no chip until the router is done Must / Should / Can tomorrows IC routers independently address these issues
Mask NRE cost ( runtimes shapes complexity) BEOL catastrophic yield loss Deposited copper can infer yield loss mechanisms Open faults more prevalent than short or bridging faults High-resistance via faults Cf. non-tree routing as long as reliability in addition to yield Variability budget as long as planarization Copper is soft dual-material polish mechanisms Oxide erosion in addition to copper dishing cross-sectional variability, inter-layer bridging faults, Low-k: thermal properties, anisotropy, nonuni as long as mity Resistivity at small conductor dimensions Whose Job Is It To Solve: The Problem: Evolution Conflicting goals Designer: freedom, reuse, migration EDA: maintenance mode Process/foundry: enhance perceived value (= add rules) Prisoners Dilemma: who will invest in change Fiddling: Incremental, linear extrapolation of current trajectory GDS-3 Thin post-processing layers (decompaction, RET insertion, ) Leads to dark future (12th Japan DA Show keynote) DAC-2003 Nanometer Futures Panel: Where should extra R&D $ be spent
The Solution: Co-Evolution Designer, EDA, in addition to process communities cooperate in addition to co-evolve to maintain the cost (value) trajectory of Moores Law Must escape Prisoners Dilemma Must be financially viable At 90nm to 65nm transition, this is a matter of survival as long as the worldwide semiconductor industry Todays Design-Manufacturing Interfaces Litho/Process (Tech. Development) Library (Library Team) Layout & libs (Corner Case Timing) Design (ASIC Chip) Mask: Dataprep (Mask House) Design Rules Device Models Tapeout Layout (collection of polygons ) RET Guardb in addition to ing all the way in all stages!! (e.g. clock ACLV guardb in addition to ~ 30%) What do we lose Per as long as mance Too much worst-casing Turnaround time Huge OPC runtimes, overdesign Predictability RET is applied post-design Mask costs Overcorrection Designers intent RET is not driven by design Foundation of the DFM Solution Bidirectional design-manufacturing data pipe Fundamental drivers: cost, value Pass functional intent to manufacturing flow Example: RET as long as predictable timing slack, leakage, yield RETs should win $$$, reduce per as long as mance variation cost-driven, parametric yield constrained RET Pass limits of manufacturing flow up to design Example: avoid corrections that cannot be manufactured or verified e.g., design should be aware of metrology N.B.: 1998-2003 papers/tutorials: http://vlsicad.ucsd.edu/~abk/TALKS/
This Tutorial Concrete examples of Manufacturing-Driven PD Deployable today Topic 1: Composability: PSM in addition to SRAF Topic 2: Per as long as mance impact limited fill insertion Topic 3: Function Aware OPC Topic 4: Library-based OPC as long as predictability Topic 5: Focus in addition to proximity-effects aware STA Some ramblings about future: regular layout, robust optimization, leakage saving without multi-Vt We will start with a manufacturing primer Outline Challenges DFM Philosophy Manufacturing in addition to Variability Primer Lithography, Masks in addition to Process Variations Design as long as Value Composability Per as long as mance Impact Limited Fill Insertion Function Aware OPC Systematic Variation Aware STA Futures of Mfg-Aware PD Photo-Lithographic Process oxidation optical mask process step photoresist coating photoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]).
Lithography Primer: Basics The famous Raleigh Equation: : Wavelength of the exposure system NA: Numerical Aperture (sine of the capture angle of the lens, in addition to is a measure of the size of the lens system) k1: process dependent adjustment factor Exposure = the amount of light or other radiant energy received per unit area of sensitized material. Depth of Focus (DOF) = a deviation from a defined reference plane wherein the required resolution as long as photolithography is still achievable. Process Window = Exposure Latitude vs. DOF plot as long as given CD tolerance Numerical Aperture NA=nsin n=refractive index as long as air, UB =1. Practical limit 0.93 NA increase DOF decrease Immersion lithography n>1 (e.g., water) Figures courtesy www.icknowledge.com k1 k1 is complex process depending on RET techniques, photoresist per as long as mance, etc Practical lower limit 0.25 Minimum resolvable dimension with 193nm steppers = 0.25193/0.93 = 52nm Source: www.icknowledge.com
RET Basics The light interacting with the mask is a wave Any wave has certain fundamental properties Wavelength () Direction Amplitude Phase RET is wavefront engineering to enhance lithography by controlling these properties Amplitude Direction Phase Courtesy F. Schellenberg, Mentor Graphics Corp. Direction: Illumination Regular Illumination Many off-axis designs (OAI) Annular Quadrupole / Quasar Dipole + OAI: Impact on PD Off axis amplifies certain pitches at the expense of the others Forbidden pitches Quasar / Quadrupole Illumination Amplifies dense 0°, 90 ° lines Destroys ±45° lines Dipole Illumination Prints only one orientation Must decompose layout as long as 2 exposures Depth of Focus Graph reference: Socha et al. Forbidden Pitches as long as 130 nm lithography in addition to below, in Optical Microlithography XIII, Proc. SPIE Vol. 4000 (2000), 1140-1155. Pitch (nm)
Conclusions Designer, physical design, in addition to mask communities must maintain cost (value) trajectory of Moores Law Wakeup call: Intel 157nm announcement Bidirectional design-mfg data pipe driven by cost, value Pass functional intent to mask in addition to foundry flows Pass limits of mask in addition to foundry flows up to design Examples Manufacturability in addition to cost/value optimization Exploitation of systematic variations (e.g., iso-dense) Composability Per as long as mance impact-limited dummy fill Intelligent mask data prep, restricted design rules, etc. Manufacturing-aware PD: much work lies ahead
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