Mellow Writes: An Everyday Experience: Sharpening a Knife A Similar Trade-off Also Works as long as Resistive Memory Write Operations!

Mellow Writes: An Everyday Experience: Sharpening a Knife A Similar Trade-off Also Works as long as Resistive Memory Write Operations! www.phwiki.com

Mellow Writes: An Everyday Experience: Sharpening a Knife A Similar Trade-off Also Works as long as Resistive Memory Write Operations!

Devine, Jill, Music Director/Midday On-Air Personality has reference to this Academic Journal, PHwiki organized this Journal Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write BacksLunkai Zhang, Diana Franklin, Frederic T. Chong1Brian Neely,Dmitri Strukov,Yuan XieAn Everyday Experience: Sharpening a KnifeDo it harshly Takes a shorter time.Bad as long as the knife.Do it gently Takes a longer time.Good as long as the knife.2A Similar Trade-off Also Works as long as Resistive Memory Write Operations!3For typical Resistive Memory technologies, slower writes are predicted to have a quadratic endurance advantage!Citation:D. B. Strukov, “Endurance-write-speed tradeoffs in nonvolatile memories,” Applied Physics A, vol. 122, no. 4, pp. 1–4, 2016.Write with higher power Takes a shorter time.Lower endurance, shorter lifetimeWrite with lower power Takes a longer time.Higher endurance, longer lifetime

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A Single Write Latency Is NOT Enough!A Single Shorter Write Latency=> Memory Lifetime suffers as long as some applications.A Single Longer Write Latency=> Per as long as mance suffers as long as some other applications.Is it possible to let a system adaptively use different write speeds, so we can improve the lifetime without loss of per as long as mance4Relatively Low Bank UtilizationMemory banks are idle as long as most of the time.Is it possible to use the bank idle time to slowly write back the data 5SchemesMellow WritesBank-Aware Mellow WritesEager Mellow WritesWear Quota6

SchemesMellow WritesBank-Aware Mellow WritesEager Mellow WritesWear Quota7Motivation: Bank Level ImbalanceBank 0 has only 1 memory block to be written back. It is less likely that the write queue will be blocked by Bank 0.8Bank 2 has more memory blocks to be written back. It is more likely that the write queue will be blocked by Bank 2. AwaitingWrites3121Bank-Aware Mellow Writes9Slow WriteNormal WriteApproach: Slowly writing back a memory block only when there is no other memory block queued as long as the same bank. AwaitingWrites3121Write back the only memory block as long as Bank 0 in slow speed.Write back current memory block as long as Bank 2 in normal speed.

Simulated SystemOoO Alpha core.32KB L1 I/D-$, 256KB L2$, 2MB L3$ (LLC).4GB Resistive Main Memory (ReRAM technology), 16 Banks, 32-entry read/write queues, write drain, Start-Gap Wear Leveling, (1.0x latency = 150ns, 1.00x endurance = 5.0 10^6 ): Norm Writes (1.0x): 1.00x latency, 1.00x enduranceSlow Writes (3.0x): 3.00x latency, 9.00x enduranceNorm Writes with no write cancellation. Slow writes with write cancellation.Eight-Year lifetime requirement.10Effectiveness of Bank-Aware Mellow Writes11No Noticeable Per as long as mance Degradation. Geomean 87% lifetime improvement compared with All-Norm.4 out of 11 applications meet the 8-year lifetime requirements.SchemesMellow WritesBank-Aware Mellow WritesEager Mellow WritesWear Quota12

So is it possible to reschedule the writesIf we can evenly reschedule the writes Wasted!Too Crowded!Motivation: Write Scheduling Imbalance in a Memory BankWith Bank-Aware Mellow Writes13Eager Mellow WritesWe predict which dirty cache lines in the Last Level Cache will not be written again be as long as e their evictions, in addition to eagerly in addition to slowly write back these cache lines.In some sense, we treat Last Level Cache as a large write buffer, in which we find proper write backs to fill the idle memory intervals.14Choosing Cache Lines as long as Eager Mellow WritesIn this paper, we choose dirty cache lines which are predicted to be useless as the c in addition to idates as long as Eager Mellow Writes. Those are, the cache lines will not be accessed again be as long as e their eviction.15Set 0Set 1Set 2Set 3Predicted uselessPredicted usefulC in addition to idates of Eager Mellow Writes if DirtyLast Level Cache

A Utility Based Approach To Predict Useless Cache LinesFor an LRU Set-associative Last Level Cache (LLC):Add an access counter as long as each LRU stack position in LLC. Increase the corresponding access counter if there is an access hit on an LRU position. For every time slice (500,000 cycles), choose the consecutive least-used LRU positions with sum less than 1/32 LLC accesses. In the next time slice, consider these cache lines with these LRU positions as useless, in addition to they can be eagerly written back.16Citation:Moinuddin K. Qureshi & Yale N. Patt, “Utility-Based Cache Partitioning: A Low-Overhead, High-Per as long as mance, Runtime Mechanism to Partition Shared Caches”, MICRO’06.Architectural Level Modifications17+ Eager Mellow Write Requests+ Eager Mellow Queue Lowest Priority, No Write Drains, Just Slow WritesEffectiveness of Eager Mellow Writes18No Per as long as mance Degradation, even some per as long as mance benefitGeomean 158% lifetime improvement compared with All-Norm.6 out of 11 applications meet the 8-year lifetime requirements.5 applications still suffer from short lifetime!

SchemesMellow WritesBank-Aware Mellow WritesEager Mellow WritesWear Quota19Partition the time into Time slices.Wear Quota (per bank): the average available wear of each time slice.20Expected LifetimeTotal Amount of Available Wear of Resistive Main MemoryWear QuotaTime SliceWear Quota21Wear QuotaTime Slice 1WearTime Slice 1Wear QuotaTime Slice 2Wear QuotaTime Slice 3Wear QuotaTime Slice 4WearTime Slice 2WearTime Slice 3WearTime Slice 4WithinWear QuotaExceedingWear QuotaWithinWear QuotaTime Slice 1: Mellow Writes Policy Time Slice 2: Mellow Writes Policy Time Slice 3: All-Slow Writes Policy Time Slice 4: Mellow Writes PolicyWithinWear Quota

Effectiveness of Wear QuotaAll 11 applications meet the 8-year lifetime requirements.22Does not degrade the per as long as mance if the lifetime requirement is already met.Degrades the per as long as mance only when necessary!How About Energy23Operation Level A 3x Slow Write consumes 66% more Energy Compared with a normal write.Total Memory Consumption of the ExecutionOn Average Less than 50% more memory energy compared with All-Norm PolicyAn Af as long as dable Cost Compared with the Lifetime Benefit.Sensitivity to Analytic ModelIn a typical ReRAM technology, compared with default speed writes, slow writes are predicted to achieve a quadratic endurance benefit. Based on a wider range of device parameters, the endurance benefit could be linear to cubic.What will happen if we have a different endurance benefitEven with a pessimistic linear endurance benefit, we can still achieve 47% lifetime improvement.24Citation:D. B. Strukov, “Endurance-write-speed tradeoffs in nonvolatile memories,” Applied Physics A, vol. 122, no. 4, pp. 1–4, 2016.

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ConclusionA new dynamic trade-off between write latency in addition to endurance.Two Mellow Writes schemes which improve the lifetime without sacrificing the per as long as mance.Wear Quota scheme which guarantees a minimal lifetime with relatively small per as long as mance loss.Low hardware overhead in addition to easy to implement.Thanks! Lunkai Zhang The University of Chicago lunkai@uchicago.edu26

Devine, Jill Music Director/Midday On-Air Personality

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