Mircea Bogdan Annie’s Central Card Status Report – 8/21/2015 The University

Mircea Bogdan  Annie’s Central Card Status Report - 8/21/2015 The University www.phwiki.com

Mircea Bogdan Annie’s Central Card Status Report – 8/21/2015 The University

Mack, Bill, On-Air Host has reference to this Academic Journal, PHwiki organized this Journal Mircea Bogdan Annie’s Central Card Status Report – 8/21/2015 The University of Chicago 6U VME32 or VME 64x Format Can work as St in addition to Alone ACC Specs General Mircea Bogdan QSFP 8 x RJ45 RJ45 Ethernet SMA USB LED VME P1 +5V VME P2 5 x SMA 16 x RJ45 or ACC Specs System Mircea Bogdan LVDS System Interface RJ45 with: LVDS Clock in 2 x LVDS In 1 x LVDS Out QSFP 8 x RJ45 RJ45 Ethernet SMA USB LED VME P1 +5V VME P2 5 x SMA 16 x RJ45 or

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Annie System Interface in addition to Clock Distribution Mircea Bogdan System Clock IN RJ45 To FPGA 1:12 Note: Clocks to FE do not come from the FPGA; Clocks to FE are fixed, not from PLL. Clocks to FE are routed to equal length (+/-2.5mm) Local Clock To FE 8 x clocks LVDS IN LVDS IN LVDS OUT ACC Specs Front End Mircea Bogdan QSFP 8 x RJ45 RJ45 Ethernet SMA USB LED VME P1 +5V VME P2 5 x SMA 16 x RJ45 or LVDS Front End Interface Each FE Unit serviced via 2xRJ45 ACC can service 4 or 8 FE Units. ACC Specs Front End Interface Mircea Bogdan LVDS Out FE LVDS Out Clock Out LVDS In LVDS In LVDS In LVDS In LVDS Out LVDS In/Out lines within one FE group are length matched to +/-5mm. (Clock Out line not included here)

Mircea Bogdan Annie Crate Master (ACM) Same module – Different Firmware ACC-0 ACC-3 ACC-7 Annie Crate Architecture Double Width ACM: One ACM Card can service 8 ACCs. System can be extended in multiples of 8, in a pyramid scheme. Single Width ACM: One ACM Card can service 4 ACCs. System can be extended in multiples of 4, in a pyramid scheme. New ACM can be designed to service up to 16 ACCs. Mircea Bogdan ACC – situation in addition to plans Questions/To Do List: Finalize Specifications; Finalize Schematic, Layout; http://edg.uchicago.edu/~bogdan/AnniesCentralCard/index.html Finalize Top Level FPGA Design; Start work on functional FPGA Design.

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