Mixed Cell-Height Implementation as long as Improved Design Quality in Advanced Nodes

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Mixed Cell-Height Implementation as long as Improved Design Quality in Advanced Nodes

Bright, Farley, Host has reference to this Academic Journal, PHwiki organized this Journal Mixed Cell-Height Implementation as long as Improved Design Quality in Advanced Nodes Sorin Dobre+, Andrew B. Kahng in addition to Jiajia Li UC San Diego VLSI CAD Laboratory+ Qualcomm Inc.OutlineBackground in addition to MotivationProblem StatementRelated WorkOur MethodologyExperimental Setup in addition to ResultsConclusionChoice of Cell Height In st in addition to ard cell-based implementation Large cell height better timing, but larger area in addition to powerSmall cell height smaller area in addition to power per gate, but large delay in addition to more buffers, pin accessibility issueCan we mix cell heights to have better tradeoffs between per as long as mance in addition to area/power better design QoR

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Post-synthesis area in addition to timing comparison among 12T-only, 8T-only in addition to mixed cell heights at 28LP12T-only tends to have large areaWeak drive strengths of 8T cells buffers areaMixing cell heights achieves >14% area reductionNo existing flow offers sub-block level mixed cell-height optimizationOur goal: mixed cell-height implementation (!) Motivation of Mixing Cell HeightsOutlineBackground in addition to MotivationProblem StatementRelated WorkOur MethodologyExperimental Setup in addition to ResultsConclusionMixed Cell-Height Placement ProblemGiven: design (i.e., gate-level netlist), timing constraints, Liberty files, in addition to floorplanPlace design such that each cell instance is legally placed in a row with corresponding height Objective: minimum design area with target per as long as mance

Challenge 1: “Chicken-Egg” LoopHeights of cell rows are defined by floorplan (site map) be as long as e placementChoices of cell heights highly depend on placement solution SynthesisFloorplanPlacementCTS/RoutingConventional design flowFloorplanPlacementChallenge 2: Area Overheads“Breaker cells” must be inserted area costVertical: P/G rail of a cell cannot encroach into adjacent-row cellsHorizontal: well-to-well spacing ruleOther layout constraints N-well sharing even number of rows in a regionAlignment with routing in addition to poly tracks“Breaker cells” must be inserted area costVertical: P/G rail of a cell cannot encroach into adjacent-row cellsHorizontal: well-to-well spacing ruleOther layout constraints N-well sharing even number of rows in a regionAlignment with routing in addition to poly tracksChallenge 2: Area OverheadsMixed cell-height implementation must comprehend these challenges

OutlineBackground in addition to MotivationProblem StatementRelated WorkOur MethodologyExperimental Setup in addition to ResultsConclusionRelated WorksNo previous work on sub-block level mixed cell-height designSimilarity to voltage isl in addition to placementAssign certain cell attribute with different values (height, Vdd)Area cost (breaker cells, level shifters)[Wu05][Ching06] propose partitioning methods to define power domains [Wu07] considers timing constraints in addition to cell placement[Guo07] embeds voltage-isl in addition to -aware optimization to partitioning-based placementMore challenges in mixed cell-height designChicken- in addition to -egg loopArea impact of cell height choices OutlineBackground in addition to MotivationProblem StatementRelated WorkOur MethodologyExperimental Setup in addition to ResultsConclusion

Overall FlowLogic SynthesisInitial placementFloorplan region definitionPlacement LegalizationFloorplan UpdateCell mappingRouting / RoutOpt / STA: with libraries of all cell heights: with revised cell LEF such that all cells have the same height (== min cell height), but scale cell width to maintain same area: based on the partition (floorplan definition) results, with cell rows of actual heights in addition to breaker cells: with commercial P&R, STA toolsExample of Overall Optimization FlowInitial placement(8T/12T cells “freely” placed)Partitioning(Yellow blocks = regions)LegalizationNew floorplanMixed-height placementTechnology: 28nm LPDesign: AESBLUE: 8T cells RED: 12T cellsFloorplan Partitioning in addition to Region DefinitionPartition block into rectangular regions with specific cell heightsDynamic programming as long as mulationcost(x1, y1, x2, y2) = total area of minority cells in region (x1, y1, x2, y2) as long as k := 1 to U as long as x1 := 0 to M, y1 := 0 to N, x2 := x1+1 to M, y2 := y1+1 to N cost (x1, y1, x2, y2, k) = min(x1 x x2, y1 y y2, 0 < t < k) { cost(x1, y1, x, y2, t) + cost(x, y1, x2, y2, k-t-1) + breaker-cell-cost , // H cuts cost(x1, y1, x2, y, t) + cost(x1, y, x2, y2, k-t-1) + breaker-cell-cost } // V cuts end as long as end as long as return min(1 k U) cost(0, 0, M, N, k)Runtime complexity = O((M+N)(MNU)2) Timing-Aware Placement LegalizationIterative optimization with two knobsCell displacement (e.g., move 8T cells from 12T region to 8T region) Cell-height swapping (e.g., size 12T cells to 8T cells in 8T region)Optimization frameworkOptimizerDisplacement of cellsSwap cells across heightsArea recoveryTiming recoverySoC EncounterECOs (displacement, gate sizing, placement legalization, trial routing) Parasitic extractionTiming analysisInternal TimerGate delay: Liberty LUTGate slew: Liberty LUTWire delay: D2MWire slew: PeriIterative Optimization FlowMapping Cells to Original Heights/WidthsRecall: In initial placement, cells have the same height (== minimum cell height), but scaled widths to maintain the same cell areaIn the updated floorplan (which have same area but different cell rows), we scale cells back to their original heights/widths in addition to map them to updated cell rows Our method (illustrated on 2D mesh)Embed mesh graphs to larger aspect ratios based on [Ellis91]Maximum (new wirelength / original wirelength) = r + 1 / r (r = original cell height / minimum cell height, e.g., as long as 12T/8T case, r = 1.5) Original cell height (hP) / min cell height (hN) = 5/4Partition area does not changeDue to scaled cell heights/widths a 5x4 mesh is embedded into a 4x5 meshCircled edge has the maximum WL increase Cell Mapping Flow (General Cases)Map cells from original floorplan to updated cell rowsPlacement density on each updated row honors original average row densityMapping procedure as long as each row R in the updated floorplan while cell density on R is less than required density Map cells in ith row of original floorplan to updated rows // sort cells in increasing order of widths ++i endwhile place mapped cells ordered by their X-coordinates in original floorplan end as long as Average wirelength penalty on 23 implementations of four designs is 0.8%OutlineBackground in addition to MotivationProblem StatementRelated WorkOur MethodologyExperimental Setup in addition to ResultsConclusionExperimental SetupDesigns: AES, MPEG (from OpenCores website)Technology: 28nm LP, dual-VT, 8T/12T ToolsSynthesis: Synopsys Design Compiler vH-2013.03-SP3P&R & timing analysis: Cadence EDI System 14.1Power analysis: Synopsys PT-PX vH-2013.06-SP2Modeling breaker cell costsHorizontal cost: 0.544m (= four placement sites)Vertical cost: 0.8m (= eight M2 pitches) Area/Per as long as mance Benefits from Mixing Cell HeightsPareto curves of power-area tradeoffUp to 25% area benefit over 12T designsUp to 20% per as long as mance benefit over 8T designsIso-per as long as mance power comparison with voltage scalingRe-optimize design if the supply voltage scaling > 30mVSimilar power with single-height designs Mixed cell height dominates in area-frequency tradeoff (previous slide)Power penalty is not captured in our cost functionPower Benefits from Mixing Cell HeightsOutlineBackground in addition to MotivationProblem StatementRelated WorkOur MethodologyExperimental Setup in addition to ResultsConclusion

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ConclusionNovel physical design optimization flow to mix cells with different heights within a single place- in addition to -route block Address the “chicken- in addition to -egg” loop between floorplan site definition in addition to the post-placement choice of cell heightsComprehend “breaker cells” area overhead in addition to layout constraints Achieve 25% area reduction, while maintaining per as long as mance, compared to single-height design flowsFuture worksMixed cell-height clock tree synthesis flowMore comprehensive cost function to trade off per as long as mance, power, area in addition to wirelengthThank you!

Bright, Farley Host

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