New Materials as long as the Gate Stack of MOS-Transistors1Presented By:Ashesh JainTuto

New Materials as long as the Gate Stack of MOS-Transistors1Presented By:Ashesh JainTuto www.phwiki.com

New Materials as long as the Gate Stack of MOS-Transistors1Presented By:Ashesh JainTuto

Davis, John, Golf Writer/Columnist has reference to this Academic Journal, PHwiki organized this Journal New Materials as long as the Gate Stack of MOS-Transistors1Presented By:Ashesh JainTutor: Dr. N in addition to ita Das GuptaIndian Institute of Technology, Delhi ContentsOverview of MOSFETsMoore’s LawProblems with thin gate oxide: Gate leakage current, Polysilicon gate depletion, Boron penetrationHigh-K oxide solutionChoice of high-K materialsPermittivity in addition to barrier heightThermodynamic stability on SiInterface qualityFilm morphologyProcess compatibilityFermi level pinning in addition to mobility degradationConclusionsNew Materials as long as the Gate Stack of MOS-Transistors2Overview of MOSFETsMOSFET has been continually scaled down in sizeReasons:Increase in drive currentHigher switching speedMore number of transistors on same real estateScaling leads to short channel effectsGate start losing control over channel chargeSiO has to be proportionally scaled to increase gate coupling with channelNew Materials as long as the Gate Stack of MOS-Transistors3

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Advantages of using SiO in addition to Poly-SiAdvantages of SiOThermodynamically stable on SiHigh quality SiO-Si interfaceInterface state density,Excellent insulator Advantages of poly-SiEasy to fabricateHigh quality poly-Si/ SiO interfaceAdjustable Fermi level by controlling dopant concentrationCompatible with both PMOS in addition to NMOSNew Materials as long as the Gate Stack of MOS-Transistors4Moore’s LawCoined by Gordon E Moore in “Cramming more components onto Integrated circuits” published in 1965“Transistor density on the chip doubles every year”SiO thickness has to be scaled @ ~0.7x every yearNew Materials as long as the Gate Stack of MOS-Transistors5Problems associated with thin SiOThickness of SiO layer required in 45nm technology is about 1.2nm (4 atomic layers deep!!)Gate oxide is running out of atomsQuantum nature of channel electron dominates.Results in:Leaky gate oxidePoly-Si gate depletionBoron penetrationNew Materials as long as the Gate Stack of MOS-Transistors6

Gate Leakage CurrentGate oxide 5 atomic layer thickQuantum Mechanical phenomenon of electron tunnelingResults in:Leakage currentPower consumptionNew Materials as long as the Gate Stack of MOS-Transistors7Ref [9]Quantum mechanical tunnelingTransition of carriers through classically as long as bidden energy states Electrons tunnel through the dielectric, even if energy barrier is higher than electron energyTwo types of tunnelingDirect Tunneling (DT)Fowler-Nordheim Tunneling:New Materials as long as the Gate Stack of MOS-Transistors8Ref [6]Direct TunnelingSignificant in thin dielectricTunnels through entire SiOTunneling current increases exponentially with decrease in oxide thicknessFowler-Nordheim Tunneling is another tunneling mechanismTake place as long as thick dielectric at sufficiently high electric fieldNew Materials as long as the Gate Stack of MOS-Transistors9Ref [10]

Gate leakage as long as 0.8nm thick gate oxideNew Materials as long as the Gate Stack of MOS-Transistors10Inversion gate leakage measurements of SiO gate oxide as long as NMOS in addition to PMOS, Ref [2]Consider this Presently a processor chip contains about 100million transistorsIf each transistor leaked a current so high Heating problems will be ensured To reduce leakage, a thicker oxide layer is required.But this means less control over channel charge Moreover:Gate leakage has direct consequences in PD-SOI MOSFETsModifies the body voltage in addition to related floating body effectsGive rise to “Gate induced floating body effects” (GIFBE)Responsible as long as kink in characteristicsNew Materials as long as the Gate Stack of MOS-Transistors11Gate DepletionIn case of thin oxide implant dose of low energy is used as long as polysilicon gatePolysilicon near the gate oxide is lightly dopedAssumption of uni as long as m doping no longer holdsThus a considerable polysilicon gate depletion effectDepletion region thickness becomes very much comparable to oxide thicknessNew Materials as long as the Gate Stack of MOS-Transistors12Doping concentration in polysilicon gate Vs distance. An annealing of 850C as long as 10min was per as long as med after the implant, Ref [1]

Contd Results in:Increase in threshold voltageDecrease in drain currentA part of the applied gate voltage falls across depletion regionNew Materials as long as the Gate Stack of MOS-Transistors13Sub threshold drain current Vs gate voltage as long as different implant conditions, Ref[1] Depletion Layer as long as mationNew Materials as long as the Gate Stack of MOS-Transistors14Boron PenetrationBoron penetrates from a P+ poly gate electrode through the thin gate oxide into the silicon substrateThreshold voltage decreasesBecomes normally onSub-threshold slope (s-factor) increasesNitridation of gate oxide prevents boron penetrationNew Materials as long as the Gate Stack of MOS-Transistors15 characteristics of boron penetrated in addition to non boron penetrated PMOS, Ref [4]BF

Key pointsNitridation:Per as long as med by RTNNitrogen concentration should be uni as long as m in addition to small at interfaceEffective in screening boron penetration down to 2nmBoron Penetration:Depends significantly on boron doseExtent of boron penetration is judged by s-factorFluorine enhances boron penetrationNew Materials as long as the Gate Stack of MOS-Transistors16Boron concentration with depthNew Materials as long as the Gate Stack of MOS-Transistors17Boron profile with different boron dose as long as pure gate oxide(PO). Annealed at 850C, Ref [4] Boron profile. Nitride oxide(NO) sample in comparison with pure oxide(PO). BF dose 1e15/cm2, Ref [4]BF DoseS-factor as long as “PO” in addition to “NO”Dependence of subthreshold slope on boron dose Pure oxide(PO): S-factor varies with boron doseNitride oxide(NO): S-factor is constant with boron doseNew Materials as long as the Gate Stack of MOS-Transistors18Sub threshold slope (s factor) dependence on BF dose as long as low temp. annealing case. = 6.5nm, Ref [4]Boron Dose

The High-K oxide solutionNew Materials as long as the Gate Stack of MOS-Transistors19To continue the scaling trendIncrease gate-channel capacitanceScaling SiO further not possibleIncrease both in addition to need to change gate oxide Choice of High-K oxideHigh-K oxide should satisfy the following properties:High Dielectric constant in addition to Barrier HeightThermodynamic stabilityInterface QualityGate compatibilityProcess CompatibilityFixed oxide chargeNew Materials as long as the Gate Stack of MOS-Transistors20Potential High-K materialsNew Materials as long as the Gate Stack of MOS-Transistors21Which one of them is appropriateDielectric constant in addition to b in addition to gap of a given material generally exhibit an inverse relationship (some materials have significant departure from this trend)Ref [5]

Permittivity in addition to Barrier HeightBarrier Height:Tunneling current is negligibleLeakage current increases exponentially with decreasing barrier heightTaO in addition to TiO have small value of in addition to hence large leakage currentHfO in addition to ZrO offer higher value of K in addition to New Materials as long as the Gate Stack of MOS-Transistors22B in addition to DiagramRef [5]B in addition to offset as long as high-k gate dielectric materialNew Materials as long as the Gate Stack of MOS-Transistors23B in addition to offset calculations as long as a number of potential High-K dielectric materials, Ref [5]Barrier HeightThermodynamic Stability on SiObservations: Most of the High-K metal oxides are unstable on SiReacts with Si to as long as m an undesirable interfacial layerInterfacial layer may alter the barrier height ( )Require an interfacial reaction barrierNeed to modify both gate in addition to channel interfaceNew Materials as long as the Gate Stack of MOS-Transistors24Reaction at TaO/Si interface resulting in as long as mation of a thin SiO layer, Ref [5]

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Schematic of two interfaceNew Materials as long as the Gate Stack of MOS-Transistors25Schematic of important regions of a field effect transistor gate stack, Ref [5]Two interface:Upper Interface: Between Gate Electrode in addition to Gate DielectricLower Interface: Between Gate Dielectric in addition to Channel Layer(Poly-Si)(High-K oxide)Interface EngineeringDeveloping reaction barriers between high-k/Si interfaceDepositing an interfacial layer of SiO or low permittivity materialReduce the extent of reaction between high-K in addition to SiHigh quality SiO-Si interface helps maintain high carrier mobilityLimits the highest possible gate stack capacitance Increased process complexityNew Materials as long as the Gate Stack of MOS-Transistors26Improved ResultsNew Materials as long as the Gate Stack of MOS-Transistors27Comparison of drive current in addition to saturation current as long as long channel PMOS transistors incorporating SiO/TaO/SiO dielectric stack, Ref [5]

Issues with Interface EngineeringFor 45nm in addition to below technology EOT~ 1nm is desired Interface layer of SiO~ 5Å thickProblems with thin interfacial layer:Extremely difficult to obtain with high qualityWill not prevent reaction between High-K in addition to SiThin interfacial layer will allow a large amount of direct electron tunneling into the high-k dielectricHigh electric field in the thin oxide can lead to charge trappingNew Materials as long as the Gate Stack of MOS-Transistors28Comparison of stacked in addition to single layer gate dielectrics in a hypothetical transistor gate stack. Either structure results in the same overall gate stack capacitance or EOT= 10Å , Ref [5]Thermodynamic stability of metal oxides on SiAlO very stable in addition to robustStable on Si against SiO as long as mationDrawback : K~ 8 – 10, hence a short term solutionFixed oxide charge at poly Si/High-K interfaceSignificant mobility degradationBoron diffuses through ALCVD AlO during dopant activation annealsNew Materials as long as the Gate Stack of MOS-Transistors29Contd TaO in addition to TiO unstable to SiO as long as mationTend to pahse separate into SiO in addition to metal oxide in addition to possibly silicide phasesZrO , HfO stable in direct contact with Si up to high temperature ZrO , HfO can be potential replacement of SiO Pseudobinary alloys in addition to are stable on Si up to high temperaturesNew Materials as long as the Gate Stack of MOS-Transistors30

References[1] R. Shireen, et al.,”Influence of polysilicon-gate depletion on the subthreshold behaviour of submicron MOSFETs”,December 2010 [online][2] R. Chau, S. Datta, M. Doczy, J. Kavalieros, in addition to M. Metz, “Gate dielectric scaling as long as high per as long as mance CMOS: from SiO2 to high-”, Extended Abstract of International Workshop on Gate Insulator, Tokyo, Japan, pp. 124–126, 2003[3] K. Mistry, et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, in addition to 100% Pb-free Packaging” in Electron Devices Meeting, 2007. IEDM 2007. IEEE International, January 2008, pp. 247-250[4] T. Morimoto, et al.,”Effects of boron penetration in addition to resultant limitations in ultra thin pure-oxide in addition to nitrided-oxide gate-films” in Electron Devices Meeting, 1990. IEDM ’90. Technical Digest., International, pp. 429-432 [5] G. Wilk, et al., “High-k gate dielectrics: Current status in addition to materials properties considerations”, Applied Physics Journal, January 2001New Materials as long as the Gate Stack of MOS-Transistors49References[6] R. Chau et al., “Advanced metal gate/high– dielectric stacks as long as high per as long as mance CMOS transistors”, in AVS 5th Int. Microelectronics Interfaces Conf., Santa Clara, CA, 2004, pp. 3–5. [7] R. Chau, et al., “Application of high- gate dielectrics in addition to metal gate electrodes to enable silicon in addition to non-silicon logic nanotechnology,” Microelectron. Eng., vol. 80, pp. 1–6, Jun. 2005[8] M. T. Bohr, R. Chau, T. Ghani in addition to K. Mistry, “The high-k solution”, IEEE Spectrum-the high-k solution, October 2007 [9]http://www.xtremesystems.org/ as long as ums/showthread.phpt=253738&page=4[ Accessed: 3rd December.2010][10] Chenming Hu, “Gate Oxide Scaling Limits in addition to Projection”, in Electron Devices Meeting, 1996. IEDM 1996 , pp. 319-322[11] http://www.iue.tuwien.ac.at/phd/entner/node23.html [Accessed: 6th December, 2010]New Materials as long as the Gate Stack of MOS-Transistors50 THANK YOU!!New Materials as long as the Gate Stack of MOS-Transistors51

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