SI as long as Free: Machine Learning of Interconnect Coupling Delay in addition to Transition Effects THANK YOU !!! BACKUP

SI as long as Free: Machine Learning of Interconnect Coupling Delay in addition to Transition Effects THANK YOU !!! BACKUP www.phwiki.com

SI as long as Free: Machine Learning of Interconnect Coupling Delay in addition to Transition Effects THANK YOU !!! BACKUP

Brascia, Dominick, Host has reference to this Academic Journal, PHwiki organized this Journal SI as long as Free: Machine Learning of Interconnect Coupling Delay in addition to Transition EffectsAndrew B. Kahng‡†, Mulong Luo†, Siddhartha Nath†‡† ECE in addition to †CSE Departments, UC San Diego{abk, muluo, sinath}@ucsd.eduOutlineMotivationPrevious WorkOur Methodology in addition to Accuracy ResultsDesign of Experiments in addition to Robustness ResultsConclusionsNon-SI to SI Calibration Use Case.sdcPost-P&R files.vSave costSave runtimeBut still accurate

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Non-SI vs. SI: How Bad is the DivergenceSlack diverges by 81ps (clock period = 1.0ns) 81ps is ~4 stages of logic at 28nm FDSOI81psPath slack in SI Mode (ns)Path Slack in Non-SI Mode (ns)Ideal correlationNon-SI to SI Calibration is Difficult!Multiple electrical, logic structure in addition to layout parametersComplex interactions between parametersBlack-box code in STA toolsElectrical parametersLogic structure parametersLayout parametersSI Timing reports:Incr delayTransition timePath delayCommercial STA toolsExample Challenge: Clock Period Dependencypath slack is 81ps at signoff clock period of 1.0nsTightening clock period to 0.82ns changes path slack to 143ps!81ps at signoff clock period143ps at tighter clock period

Example Challenge: Ground Capacitance DependencyIncremental transition time (DTran) increases but incremental delay (SI Incr Delay) due to SI decreasesThis anti-correlation is non-obvious! 14ps15psOur ContributionsIdentify multiple sources of timing divergence between non-SI in addition to SI modesProvide new insights in terms of modeling parameters required to calibrate non-SI to SI timingDevelop new models to calibrate non-SI to SI timing using machine learning-based techniquesDemonstrate accuracy in addition to robustness of our models on a variety of testcasesWorst-case divergence of 5.2ps in incremental delay due to SIWorst-case divergence of 8.2ps in SI-aware path delayOutlineMotivationPrevious WorkOur Methodology in addition to Accuracy ResultsDesign of Experiments in addition to Robustness ResultsConclusions

Review of Previous WorksAnalytical SI-induced delay modelsSapatnekar2000Lumps coupling capacitance to ground capacitance using Miller coupling factorsUses an iterative algorithm to estimate crosstalk delay on netsXiao2000Derive a two-pole model as long as crosstalk noise computation using iterative Newton-Raphson methodCorrelation of STA toolsThiel2004Correlate SPICE to PT timing reportsKahng2013Propose an offset-based correlation in addition to wire delay estimation using linear regression to calibrate path slacks with PTHan2014Develop machine learning models to correlate SI to SI in addition to non-SI to non-SI timing between STA tools, in addition to STA in addition to design implementation toolsMiscorrelations of Han2014Calibrate non-SI to non-SI or SI to SISignoff timer to signoff timerSignoff timer to IC implementation toolsDivergence of 60ps when trying to calibrate non-SI to SIWe need new models to calibrate SI from non-SI!OutlineMotivationPrevious WorkOur Methodology in addition to Accuracy ResultsDesign of Experiments in addition to Robustness ResultsConclusions

Identifying Modeling ParametersNeed to consider new electrical parametersRw is the resistance of an arcCc is the coupling capacitance of an arcLE is the logic ef as long as t of a driverThus, RW, Cc, LE have great impacts on timing, we identify them as parameters as long as incremental delay in SI modeRw x CcIncremental Delay in SI Mode (ns)LEIncremental Delay in SI Mode (ns)List of Modeling ParametersIncremental transition time due to SIIncremental delay due to SISI-aware path delayElectrical, logic structure, in addition to layout parameters in addition to constraintSeveral new electrical, logic structure, layout parametersComparison between ModelsHan2014 models have worst-case path delay error of 87.3ps vs. 8.2ps error from our models

Modeling FlowTiming Reports in SI ModeTiming Reports in Non-SI ModeCreate Training, Validation in addition to Testing SetsANN (2 Hidden Layers, 5-Fold Cross-Validation)Save Model in addition to ExitSVM (RBF Kernel, 5-Fold Cross-Validation)HSM(Weighted Predictions from ANN in addition to SVM)Linear regression cannot capture complex interactions between parametersNon-linear techniques capture these interactions using hidden parametersIncremental Transition Time (Due to SI) ModelIncremental Transition Time (Due to SI): Transition Time considering SI – Transition Time w/o SIWe use six modeling parametersAccuracy of Incremental Transition Time PredictionWorst-case absolute error of 7.0ps (8.8%)Range of errors is 11.3psAverage absolute error of 0.7ps (0.6%)Actual Incremental Transition Time (ps)Predicted Incremental Transition Time (ps)7.0psIdeal correlation

Incremental Delay (Due to SI) ModelIncremental Delay (Due to SI): Delay considering SI – Delay w/o SIWe use 11 modeling parametersAccuracy of Incremental Delay PredictionWorst-case absolute error of 5.2ps (15.7%)Range of errors is 9.8psAverage absolute error of 1.2ps (1.1%)Actual SI Incr Delay (ps)Predicted SI Incr Delay (ps)5.2psIdeal correlationSI-Aware Path Delay ModelWe use three modeling parameters

Accuracy of Path Delay PredictionWorst-case absolute error of 8.2ps (6.9%)Average absolute error of 1.7ps (1.4%)Actual Path Delay (ps)Predicted Path Delay (ps)8.2psIdeal correlationOutlineMotivationPrevious WorkOur Methodology in addition to Accuracy ResultsDesign of Experiments in addition to Robustness ResultsConclusionsTestcasesWe use real open-source designs in addition to artificial testcasesTechnology: 28nm foundry FDSOITotal data points: 188K

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Artificial TestcasesSTA Tool FlowsRead databases of timing librariesRead in addition to link design (post-P&R netlist)Read constraints (.sdc) in addition to parasitics (.spef)In non-SI mode, use MCF to add coupling cap to ground capIn SI mode, set flags to not reselect critical path as long as SI analysis, select clock nets in addition to delay analysis mode as edge-alignedPer as long as m path-based timing analysis of top-1K pathsObtain detailed timing reportsRobustness of ModelsNew implementation of JPEG has different clock period, stages, utilizationWorst-case absolute error of 7.9ps (12.3%)Average absolute error of 1.6ps (2.6%)Actual SI Incr Delay (ps)Predicted SI Incr Delay (ps)7.9psIdeal correlation

OutlineMotivationPrevious WorkOur Methodology in addition to Accuracy ResultsDesign of Experiments in addition to Robustness ResultsConclusionsConclusionsCalibration of non-SI to SI enables cost in addition to runtime savings as long as SoC design teamsWe analyze electrical, logic structure in addition to layout parameters that cause timing divergence between non-SI in addition to SI modesWe develop machine learning-based models to accurately calibrate non-SI to SI timingOur models have a worst-case error of 8.2ps Si-aware path delay in a 28nm foundry FDSOI technologyOngoingCorrelate graph-based in addition to path-based timing analysisIntegrate our models with an academic timerTHANK YOU!!!Our thanks to Dr. Tuck-Boon Chan of Qualcomm Inc. in addition to Ms. Nancy MacDonald of Broadcom Corp.BACKUP

Han2014 Modeling ParametersWhy Bother About SI vs. Non-SI CalibrationCan we calibrate SI to non-SI to reduce cost in addition to runtime

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