Toward Quantifying the IC Design Value of Interconnect Technology ImprovementTuc

Toward Quantifying the IC Design Value of Interconnect Technology ImprovementTuc www.phwiki.com

Toward Quantifying the IC Design Value of Interconnect Technology ImprovementTuc

Blalock, Charles, Host has reference to this Academic Journal, PHwiki organized this Journal Toward Quantifying the IC Design Value of Interconnect Technology ImprovementTuck-Boon Chan, Andrew B. Kahng, Jiajia Li VLSI CAD LABORATORY, UC San Diegohttp://vlsicad.ucsd.eduOutlineMotivationRelated WorkOur FrameworkExperiments in addition to ResultsConclusionOutlineMotivationRelated WorkOur FrameworkExperiments in addition to ResultsConclusion

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MotivationWire delay increases with technology scalingImprovement of BEOL both important in addition to expensiveIssue 1: no systematic quantification of ROI from BEOL improvement Issue 2: unclear whether BEOL improvement benefits can be leveraged by EDA toolsGoals:A framework to quantify BEOL improvement values guide BEOL technology investment in addition to targetsAssess EDA tools’ ability to leverage improved BEOL = potential “EDA gap” Focus of Our WorkProduct quality comes from interaction among design, BEOL technology, EDA toolWe focus on interaction between BEOL in addition to EDA OutlineMotivationRelated WorkOur FrameworkExperiments in addition to ResultsConclusion

Related WorkStudies of DRAM or simple logic circuits, not at chip-level Ignores interaction between BEOL technology, EDA tool[Li01] – DRAM per as long as mance improvements from low-k[Kapur02] – R, C impacts on signal, power[Bamal06] – Per as long as mance, energy comparison studies with different interconnect technologiesFocus on variation, not future BEOL improvements[Jeong10] – Chip-level impacts of interconnect variation due to double-patterning OutlineMotivationRelated WorkOur FrameworkExperiments in addition to ResultsConclusionOur Framework Modify BEOL files to model R, C reductions in future technologiesModify ITF files Use Synopsys StarRC to convert ITF to TLUplus filesDesign implementation (RTL-to-layout in addition to signoff) with original in addition to modified BEOL filesRun timing, power analysis

TestbedDesigns: {aes-cipher, des-perf, mpeg2, pci-bridge32} from OpenCores x {fast, slow} clock periodsTechnology: TSMC 45nm, LVT in addition to HVT20SOC in addition to below can be very differentSP&R: Synopsys Design Compiler + IC Compiler Execute each P&R run three times denoisingTiming in addition to power analysis: Synopsys IC CompilerSignoff: no hold or EM violation, TNS < 30ps Apples-to-apples comparison as long as design metricsOutlineMotivationRelated WorkOur FrameworkExperiments in addition to ResultsConclusionExpt 1: Impact of R, C Reduction on Power45% R, C reduction only leads to 8% power reductionR, C reduction improves timing fewer / smaller cells leakage power (but, only on critical paths)C reduction load cap net switching power (but, gate cap dominates)R, C=%: implementation with % dielectric constant in addition to metal resistivity w.r.t original BEOLR, C reduction occurs on M2-M5 Power of implementation with original BEOL Impact of R, C Reduction on AreaR, C reduction leads to little improvement in areaTool uses Vt swapping to exploit improved timingSame footprint of LVT in addition to HVT cells same post-opt areaOptimization methodology of EDA tools affects value extracted from improved BEOL Area of implementation with original BEOLExpt 2: Reduction in R vs. in CIn this experiment, C reduction offers more benefitsWire delay trade timing as long as powerR reduction improves wire delayC reduction improves wire delay + load capR reduction can be critical with high Vdd, temperatureTechnology R&D might focus more on C reductionPower w/ only R reductionPower w/ only C reductionExpt 3: R, C Reduction in Advanced TechnologyWire delay becomes critical in advanced technologiesImpact of R reduction increasesWe model advanced technology = increase R by 8xBenefits of R, C reduction increase in advanced technologiesLeakage powerTotal power Expt 4: Impact of Layer SelectionBEOL improvement incurs high manufacturing costWhat is optimum subset of layers to improve under cost limitsFlexible BEOL = subset of layers is selectively improvedInappropriate selection of R, C-reduced layers is suboptimal Guideline: reduce R, C on adjacent in addition to highly utilized layersSmall difference between different layer selectionsTools’ ability to leverage the improved BEOL layersTools’ Exploitation of R, C ReductionAssessment flowImplement designs with both original in addition to improved BEOLRun timing in addition to power analysis with improved BEOLCompare frequency, powerPreliminary results show tool can leverage R, C reductionCase 1 might be misguided during optimization Reduced R, C on M3, M4Reduced R, C on M2, M5RC-Awareness in EDA ToolsA “smart” router should be aware of improved BEOLRoute setup critical paths on layers with small R, CRoute hold critical paths on layers with large R, Cwire distribution (of layer x) = %wire on layer x - %wire on layer x Assessment: Implement designs with flexible BEOL Check wire distribution of layers as long as setup- in addition to hold-critical nets Experimental ResultsCompare wire distribution from current router (bars) in addition to a hypothetical RC-aware router (ovals)White (Orange) = positive (negative) wire distribution Same color of bar in addition to dotted oval RC-awarenessRouter is not fully responsive to BEOL R, C reduction Setup-critical netsHold-critical netsOutlineMotivationRelated WorkOur FrameworkExperiments in addition to ResultsConclusionConclusionFramework to quantify impact of interconnect resistance in addition to /or capacitance reductions on chip-level design metricsReduction in capacitance gives more benefits than in resistanceR reduction can be critical in wire-delay dominant designs (due to high Vdd, temperature or advanced technology) Capability of EDA tools to leverage improved BEOL has room as long as improvement Ongoing worksIso-constraints vs. iso-GDS ISO-GDS ExptBasic tradeoffs to exploit improved BEOLR, C reduction improved timing Vdd Power Frequency improvementVdd reductionPower reductionR, C reductionR, C reductionR, C reductionGate-wire balancePer as long as mance requirement+ device type Activity factor + nominal voltage + device typeConclusionFramework to quantify impact of interconnect resistance in addition to /or capacitance reductions on chip-level design metricsReduction in capacitance gives more benefits than in resistanceR reduction can be critical in wire-delay dominant designs (due to high Vdd, temperature or advanced technology) Capability of EDA tools to leverage improved BEOL has room as long as improvement Ongoing worksIso-constraints vs. iso-GDSStudy impact of interconnect R, C reduction across wide supply voltagesExtend our analyses to M1 in addition to middle-of-line layersAcknowledgmentsWork supported from S in addition to ia National Labs, Qualcomm, Samsung, NSF, SRC, the IMPACT (UC Discovery) in addition to IMPACT+ centers Blalock, Charles WTLS-AM Host www.phwiki.com

Thank You!Backup SlidesValues of Improved BEOLQuestion 1: What is overall impact of R in addition to /or C reduction(s) on design metrics45% R, C reduction 8% power reduction, similar areaQuestion 2: Which reductions offer more benefits, in R or in CC reduction offers more benefitsR reduction can be critical with high Vdd, temperatureQuestion 3: How will impacts of R, C reduction change in advanced technology nodesBenefits of R, C reduction increase in advanced technologyQuestion 4: What is optimum subset of layers to improve under cost limitsShould reduce R, C on adjacent in addition to highly utilized layers

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