Ultimate Device Scaling: Intrinsic Per as long as mance Comparisons of Carbon-based, InGa

Ultimate Device Scaling: Intrinsic Per as long as mance Comparisons of Carbon-based, InGa www.phwiki.com

Ultimate Device Scaling: Intrinsic Per as long as mance Comparisons of Carbon-based, InGa

Born, Lee, Meteorologist has reference to this Academic Journal, PHwiki organized this Journal Ultimate Device Scaling: Intrinsic Per as long as mance Comparisons of Carbon-based, InGaAs, in addition to Si Field-effect Transistors as long as 5 nm Gate Length Mathieu Luisier1, Mark Lundstrom2, Dimitri Antoniadis3, in addition to Jeffrey Bokor4 1ETH Zurich, 2Purdue University, 3MIT, in addition to 4University of Cali as long as nia at Berkeley Outline Motivation

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Motivation: Future of Moore’s Law 65nm (2005) 45nm (2007) 32nm (2009) 22nm (2011) 5nm (2020) Source: Intel Corporation 3-D Si FinFETs as long as ever What will be the dominant limiting factors when Lg<10nm Gate Length Reduction in planar Si MOSFETs: => increase of short-channel effects (SCE) => poor electrostatic control (single-gate) Gate Length Reduction in planar Si MOSFETs: => increase of short-channel effects (SCE) => poor electrostatic control (single-gate) => SOLUTION: 3-D FinFET since 2011 Leakage Sources in Ultrascaled Devices IBT/ S-to-D BTBT1 BTBT2 HIBL B in addition to Diagram of Lg=5nm Nano-transistor How can we minimize leakage Best device structure at Lg=5nm: The least sensitive to leakage P. Hashemi et al., EDL 30, 401 (2009) L. Tapasztó et al., Nat. Nano. 3, 397 (2008) Y.Q. Wu et al., EDL 30, 700 (2009) Nanowire Graphene III-V UTB CNT NEEDED: Fast, cheap, in addition to reliable plat as long as m to investigate the per as long as mance of next-generation ultrascaled nano-transistors beyond 3-D FinFETs Supratik Guha, IBM Research

Simulation Approach More Features Simulation Capabilities Efficient Parallel Computing 3D Quantum Transport Solver Different Flavors of Atomistic Tight-Binding Models Multi-Physics Modeling: From Ballistic to Dissipative (e-ph) Electron/Hole Transport Industrial-Strength Nano-electronic Device Simulator Multi-Geometry Capabilities Investigate Per as long as mance of Ultra-Scaled Nano-Devices be as long as e Fabrication Schrödinger-Poisson Solver with NEGF in addition to WF Finite Element Poisson Accelerate Simulation Time through Massive in addition to Multi-Level Parallelization State-of-the-art Nano-TCAD Tool Physical Models Si B in addition to structure TB: sp3d5s Bias Momentum Energy Space Model Verifications Expt: J. del Alamo @ MIT Expt: A. Franklin @ IBM YH Expt: S. Rommel @ RIT S. Datta @ PSU III-V HEMT CNT FET BTBT Diode Zener Current NDR Current For more in as long as mation, see presentation 23.7 by Aaron Franklin: “Sub-10 nm Carbon Nanotube Transistor”

General Scaling Considerations Device Characteristics CNT NW SG-AGNR DG-AGNR DG-UTB Id-Vgs at Vds=0.5 V in Carbon Devices AGNR width: 2.1 nm / CNT diameter: 1.49 nm / B in addition to Gap Eg=0.56 eV Observations: same EOT gives very different electrostatic gate-channel coupling as long as Eg>Vds, BTBT remains weak, but still intra-b in addition to tunneling SiO2 EOT=0.64nm HfO2 EOT=0.64nm BTBT HIBL/IBT

Intra-B in addition to Tunneling: Electrostatics Spectral current through GAA CNT FETs with d=1.49 nm, Eg=0.563 eV, different dielectrics, in addition to EOT=0.64 nm Fringing Fields: stronger when spacer with large R effective channel length is longer same effect as gate underlap doping Intra-B in addition to Tunneling: Material (1) Fix electrostatic potential (Gaussian-like barrier) Investigate how semiconductor properties influence IBT CNT d=1nm Eg=0.817eV Si NW d=3nm Eg=1.404eV Id=4.4nA Id=91nA Smaller b in addition to gap ( in addition to m) gives higher intra-b in addition to tunneling current Need to underst in addition to why OBSERVATIONS: Current flows through the potential barrier, almost no thermionic component Intra-B in addition to Tunneling: Material (2) What is needed: Under-the-Barrier (UB) model Same principle as Top-of-the-Barrier (ToB), but with Complex B in addition to structure instead of Real B in addition to structure Transmission through potential barrier: T(E)=exp(-2(E)L) ToB UB Eg=1.408eV Eg=1.404eV Eg=1.378eV Eg=0.817eV

Ohmic vs Schottky Contacts Ohmic Schottky Id-Vgs transfer characteristics as long as Si NW in addition to CNT FETs with Ohmic in addition to Schottky Contacts Per as long as mance Comparisons Id-Vgs at Vds=0.5 V in CNT, NW, in addition to UTB VDD=0.5 V Features: CNT with d=0.6nm in addition to Si/InGaAs NW with d=3nm have same b in addition to gap: Eg=1.4eV CNT with d=1nm has b in addition to gap: Eg=0.82eV EOT=0.64nm made of 3.3nm HfO2 No AGNR since worse than CNT Intrinsic characteristics d=1nm GAA-CNT (high IBT) in addition to DG-UTB (bad electrostatics) scale poorly 3-D devices with same “large” b in addition to gap (Eg=1.4 eV) scale better (low IBT) if CNT with d<1 nm in addition to Eg>1 eV possible, then at least as good as NW CHALLENGE: trade-off between high injection velocity (low m) in addition to low SS (high m) needed, new constraint at short gate lengths

Conclusion Conclusion in addition to Outlook

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